1/* 2 * Etrax general port I/O device 3 * 4 * Copyright (c) 1999-2007 Axis Communications AB 5 * 6 * Authors: Bjorn Wesen (initial version) 7 * Ola Knutsson (LED handling) 8 * Johan Adolfsson (read/set directions, write, port G) 9 */ 10 11 12#include <linux/module.h> 13#include <linux/sched.h> 14#include <linux/slab.h> 15#include <linux/ioport.h> 16#include <linux/errno.h> 17#include <linux/kernel.h> 18#include <linux/fs.h> 19#include <linux/string.h> 20#include <linux/poll.h> 21#include <linux/init.h> 22#include <linux/interrupt.h> 23 24#include <asm/etraxgpio.h> 25#include <arch/svinto.h> 26#include <asm/io.h> 27#include <asm/system.h> 28#include <asm/irq.h> 29#include <arch/io_interface_mux.h> 30 31#define GPIO_MAJOR 120 /* experimental MAJOR number */ 32 33#define D(x) 34 35#define DP(x) 36 37static char gpio_name[] = "etrax gpio"; 38 39 40static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 41static ssize_t gpio_write(struct file *file, const char __user *buf, 42 size_t count, loff_t *off); 43static int gpio_open(struct inode *inode, struct file *filp); 44static int gpio_release(struct inode *inode, struct file *filp); 45static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait); 46 47/* private data per open() of this driver */ 48 49struct gpio_private { 50 struct gpio_private *next; 51 /* These fields are for PA and PB only */ 52 volatile unsigned char *port, *shadow; 53 volatile unsigned char *dir, *dir_shadow; 54 unsigned char changeable_dir; 55 unsigned char changeable_bits; 56 unsigned char clk_mask; 57 unsigned char data_mask; 58 unsigned char write_msb; 59 unsigned char pad1, pad2, pad3; 60 /* These fields are generic */ 61 unsigned long highalarm, lowalarm; 62 wait_queue_head_t alarm_wq; 63 int minor; 64}; 65 66/* linked list of alarms to check for */ 67 68static struct gpio_private *alarmlist; 69 70static int gpio_some_alarms; /* Set if someone uses alarm */ 71static unsigned long gpio_pa_irq_enabled_mask; 72 73static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */ 74 75/* Port A and B use 8 bit access, but Port G is 32 bit */ 76#define NUM_PORTS (GPIO_MINOR_B+1) 77 78static volatile unsigned char *ports[NUM_PORTS] = { 79 R_PORT_PA_DATA, 80 R_PORT_PB_DATA, 81}; 82static volatile unsigned char *shads[NUM_PORTS] = { 83 &port_pa_data_shadow, 84 &port_pb_data_shadow 85}; 86 87/* What direction bits that are user changeable 1=changeable*/ 88#ifndef CONFIG_ETRAX_PA_CHANGEABLE_DIR 89#define CONFIG_ETRAX_PA_CHANGEABLE_DIR 0x00 90#endif 91#ifndef CONFIG_ETRAX_PB_CHANGEABLE_DIR 92#define CONFIG_ETRAX_PB_CHANGEABLE_DIR 0x00 93#endif 94 95#ifndef CONFIG_ETRAX_PA_CHANGEABLE_BITS 96#define CONFIG_ETRAX_PA_CHANGEABLE_BITS 0xFF 97#endif 98#ifndef CONFIG_ETRAX_PB_CHANGEABLE_BITS 99#define CONFIG_ETRAX_PB_CHANGEABLE_BITS 0xFF 100#endif 101 102 103static unsigned char changeable_dir[NUM_PORTS] = { 104 CONFIG_ETRAX_PA_CHANGEABLE_DIR, 105 CONFIG_ETRAX_PB_CHANGEABLE_DIR 106}; 107static unsigned char changeable_bits[NUM_PORTS] = { 108 CONFIG_ETRAX_PA_CHANGEABLE_BITS, 109 CONFIG_ETRAX_PB_CHANGEABLE_BITS 110}; 111 112static volatile unsigned char *dir[NUM_PORTS] = { 113 R_PORT_PA_DIR, 114 R_PORT_PB_DIR 115}; 116 117static volatile unsigned char *dir_shadow[NUM_PORTS] = { 118 &port_pa_dir_shadow, 119 &port_pb_dir_shadow 120}; 121 122/* All bits in port g that can change dir. */ 123static const unsigned long int changeable_dir_g_mask = 0x01FFFF01; 124 125/* Port G is 32 bit, handle it special, some bits are both inputs 126 and outputs at the same time, only some of the bits can change direction 127 and some of them in groups of 8 bit. */ 128static unsigned long changeable_dir_g; 129static unsigned long dir_g_in_bits; 130static unsigned long dir_g_out_bits; 131static unsigned long dir_g_shadow; /* 1=output */ 132 133#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B) 134 135 136static unsigned int gpio_poll(struct file *file, poll_table *wait) 137{ 138 unsigned int mask = 0; 139 struct gpio_private *priv = file->private_data; 140 unsigned long data; 141 unsigned long flags; 142 143 spin_lock_irqsave(&gpio_lock, flags); 144 145 poll_wait(file, &priv->alarm_wq, wait); 146 if (priv->minor == GPIO_MINOR_A) { 147 unsigned long tmp; 148 data = *R_PORT_PA_DATA; 149 /* PA has support for high level interrupt - 150 * lets activate for those low and with highalarm set 151 */ 152 tmp = ~data & priv->highalarm & 0xFF; 153 tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR); 154 155 gpio_pa_irq_enabled_mask |= tmp; 156 *R_IRQ_MASK1_SET = tmp; 157 } else if (priv->minor == GPIO_MINOR_B) 158 data = *R_PORT_PB_DATA; 159 else if (priv->minor == GPIO_MINOR_G) 160 data = *R_PORT_G_DATA; 161 else { 162 mask = 0; 163 goto out; 164 } 165 166 if ((data & priv->highalarm) || 167 (~data & priv->lowalarm)) { 168 mask = POLLIN|POLLRDNORM; 169 } 170 171out: 172 spin_unlock_irqrestore(&gpio_lock, flags); 173 DP(printk("gpio_poll ready: mask 0x%08X\n", mask)); 174 175 return mask; 176} 177 178int etrax_gpio_wake_up_check(void) 179{ 180 struct gpio_private *priv; 181 unsigned long data = 0; 182 int ret = 0; 183 unsigned long flags; 184 185 spin_lock_irqsave(&gpio_lock, flags); 186 priv = alarmlist; 187 while (priv) { 188 if (USE_PORTS(priv)) 189 data = *priv->port; 190 else if (priv->minor == GPIO_MINOR_G) 191 data = *R_PORT_G_DATA; 192 193 if ((data & priv->highalarm) || 194 (~data & priv->lowalarm)) { 195 DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor)); 196 wake_up_interruptible(&priv->alarm_wq); 197 ret = 1; 198 } 199 priv = priv->next; 200 } 201 spin_unlock_irqrestore(&gpio_lock, flags); 202 return ret; 203} 204 205static irqreturn_t 206gpio_poll_timer_interrupt(int irq, void *dev_id) 207{ 208 if (gpio_some_alarms) { 209 etrax_gpio_wake_up_check(); 210 return IRQ_HANDLED; 211 } 212 return IRQ_NONE; 213} 214 215static irqreturn_t 216gpio_interrupt(int irq, void *dev_id) 217{ 218 unsigned long tmp; 219 unsigned long flags; 220 221 spin_lock_irqsave(&gpio_lock, flags); 222 223 /* Find what PA interrupts are active */ 224 tmp = (*R_IRQ_READ1); 225 226 /* Find those that we have enabled */ 227 tmp &= gpio_pa_irq_enabled_mask; 228 229 /* Clear them.. */ 230 *R_IRQ_MASK1_CLR = tmp; 231 gpio_pa_irq_enabled_mask &= ~tmp; 232 233 spin_unlock_irqrestore(&gpio_lock, flags); 234 235 if (gpio_some_alarms) 236 return IRQ_RETVAL(etrax_gpio_wake_up_check()); 237 238 return IRQ_NONE; 239} 240 241static void gpio_write_bit(struct gpio_private *priv, 242 unsigned char data, int bit) 243{ 244 *priv->port = *priv->shadow &= ~(priv->clk_mask); 245 if (data & 1 << bit) 246 *priv->port = *priv->shadow |= priv->data_mask; 247 else 248 *priv->port = *priv->shadow &= ~(priv->data_mask); 249 250 /* For FPGA: min 5.0ns (DCC) before CCLK high */ 251 *priv->port = *priv->shadow |= priv->clk_mask; 252} 253 254static void gpio_write_byte(struct gpio_private *priv, unsigned char data) 255{ 256 int i; 257 258 if (priv->write_msb) 259 for (i = 7; i >= 0; i--) 260 gpio_write_bit(priv, data, i); 261 else 262 for (i = 0; i <= 7; i++) 263 gpio_write_bit(priv, data, i); 264} 265 266static ssize_t gpio_write(struct file *file, const char __user *buf, 267 size_t count, loff_t *off) 268{ 269 struct gpio_private *priv = file->private_data; 270 unsigned long flags; 271 ssize_t retval = count; 272 273 if (priv->minor != GPIO_MINOR_A && priv->minor != GPIO_MINOR_B) 274 return -EFAULT; 275 276 if (!access_ok(VERIFY_READ, buf, count)) 277 return -EFAULT; 278 279 spin_lock_irqsave(&gpio_lock, flags); 280 281 /* It must have been configured using the IO_CFG_WRITE_MODE */ 282 /* Perhaps a better error code? */ 283 if (priv->clk_mask == 0 || priv->data_mask == 0) { 284 retval = -EPERM; 285 goto out; 286 } 287 288 D(printk(KERN_DEBUG "gpio_write: %02X to data 0x%02X " 289 "clk 0x%02X msb: %i\n", 290 count, priv->data_mask, priv->clk_mask, priv->write_msb)); 291 292 while (count--) 293 gpio_write_byte(priv, *buf++); 294 295out: 296 spin_unlock_irqrestore(&gpio_lock, flags); 297 return retval; 298} 299 300 301 302static int 303gpio_open(struct inode *inode, struct file *filp) 304{ 305 struct gpio_private *priv; 306 int p = iminor(inode); 307 unsigned long flags; 308 309 if (p > GPIO_MINOR_LAST) 310 return -EINVAL; 311 312 priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL); 313 314 if (!priv) 315 return -ENOMEM; 316 317 priv->minor = p; 318 319 /* initialize the io/alarm struct */ 320 321 if (USE_PORTS(priv)) { /* A and B */ 322 priv->port = ports[p]; 323 priv->shadow = shads[p]; 324 priv->dir = dir[p]; 325 priv->dir_shadow = dir_shadow[p]; 326 priv->changeable_dir = changeable_dir[p]; 327 priv->changeable_bits = changeable_bits[p]; 328 } else { 329 priv->port = NULL; 330 priv->shadow = NULL; 331 priv->dir = NULL; 332 priv->dir_shadow = NULL; 333 priv->changeable_dir = 0; 334 priv->changeable_bits = 0; 335 } 336 337 priv->highalarm = 0; 338 priv->lowalarm = 0; 339 priv->clk_mask = 0; 340 priv->data_mask = 0; 341 init_waitqueue_head(&priv->alarm_wq); 342 343 filp->private_data = priv; 344 345 /* link it into our alarmlist */ 346 spin_lock_irqsave(&gpio_lock, flags); 347 priv->next = alarmlist; 348 alarmlist = priv; 349 spin_unlock_irqrestore(&gpio_lock, flags); 350 351 return 0; 352} 353 354static int 355gpio_release(struct inode *inode, struct file *filp) 356{ 357 struct gpio_private *p; 358 struct gpio_private *todel; 359 unsigned long flags; 360 361 spin_lock_irqsave(&gpio_lock, flags); 362 363 p = alarmlist; 364 todel = filp->private_data; 365 366 /* unlink from alarmlist and free the private structure */ 367 368 if (p == todel) { 369 alarmlist = todel->next; 370 } else { 371 while (p->next != todel) 372 p = p->next; 373 p->next = todel->next; 374 } 375 376 kfree(todel); 377 /* Check if there are still any alarms set */ 378 p = alarmlist; 379 while (p) { 380 if (p->highalarm | p->lowalarm) { 381 gpio_some_alarms = 1; 382 goto out; 383 } 384 p = p->next; 385 } 386 gpio_some_alarms = 0; 387out: 388 spin_unlock_irqrestore(&gpio_lock, flags); 389 return 0; 390} 391 392/* Main device API. ioctl's to read/set/clear bits, as well as to 393 * set alarms to wait for using a subsequent select(). 394 */ 395unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg) 396{ 397 /* Set direction 0=unchanged 1=input, 398 * return mask with 1=input */ 399 if (USE_PORTS(priv)) { 400 *priv->dir = *priv->dir_shadow &= 401 ~((unsigned char)arg & priv->changeable_dir); 402 return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */ 403 } 404 405 if (priv->minor != GPIO_MINOR_G) 406 return 0; 407 408 /* We must fiddle with R_GEN_CONFIG to change dir */ 409 if (((arg & dir_g_in_bits) != arg) && 410 (arg & changeable_dir_g)) { 411 arg &= changeable_dir_g; 412 /* Clear bits in genconfig to set to input */ 413 if (arg & (1<<0)) { 414 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g0dir); 415 dir_g_in_bits |= (1<<0); 416 dir_g_out_bits &= ~(1<<0); 417 } 418 if ((arg & 0x0000FF00) == 0x0000FF00) { 419 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g8_15dir); 420 dir_g_in_bits |= 0x0000FF00; 421 dir_g_out_bits &= ~0x0000FF00; 422 } 423 if ((arg & 0x00FF0000) == 0x00FF0000) { 424 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g16_23dir); 425 dir_g_in_bits |= 0x00FF0000; 426 dir_g_out_bits &= ~0x00FF0000; 427 } 428 if (arg & (1<<24)) { 429 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g24dir); 430 dir_g_in_bits |= (1<<24); 431 dir_g_out_bits &= ~(1<<24); 432 } 433 D(printk(KERN_DEBUG "gpio: SETINPUT on port G set " 434 "genconfig to 0x%08lX " 435 "in_bits: 0x%08lX " 436 "out_bits: 0x%08lX\n", 437 (unsigned long)genconfig_shadow, 438 dir_g_in_bits, dir_g_out_bits)); 439 *R_GEN_CONFIG = genconfig_shadow; 440 /* Must be a >120 ns delay before writing this again */ 441 442 } 443 return dir_g_in_bits; 444} /* setget_input */ 445 446unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg) 447{ 448 if (USE_PORTS(priv)) { 449 *priv->dir = *priv->dir_shadow |= 450 ((unsigned char)arg & priv->changeable_dir); 451 return *priv->dir_shadow; 452 } 453 if (priv->minor != GPIO_MINOR_G) 454 return 0; 455 456 /* We must fiddle with R_GEN_CONFIG to change dir */ 457 if (((arg & dir_g_out_bits) != arg) && 458 (arg & changeable_dir_g)) { 459 /* Set bits in genconfig to set to output */ 460 if (arg & (1<<0)) { 461 genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g0dir); 462 dir_g_out_bits |= (1<<0); 463 dir_g_in_bits &= ~(1<<0); 464 } 465 if ((arg & 0x0000FF00) == 0x0000FF00) { 466 genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g8_15dir); 467 dir_g_out_bits |= 0x0000FF00; 468 dir_g_in_bits &= ~0x0000FF00; 469 } 470 if ((arg & 0x00FF0000) == 0x00FF0000) { 471 genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g16_23dir); 472 dir_g_out_bits |= 0x00FF0000; 473 dir_g_in_bits &= ~0x00FF0000; 474 } 475 if (arg & (1<<24)) { 476 genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g24dir); 477 dir_g_out_bits |= (1<<24); 478 dir_g_in_bits &= ~(1<<24); 479 } 480 D(printk(KERN_INFO "gpio: SETOUTPUT on port G set " 481 "genconfig to 0x%08lX " 482 "in_bits: 0x%08lX " 483 "out_bits: 0x%08lX\n", 484 (unsigned long)genconfig_shadow, 485 dir_g_in_bits, dir_g_out_bits)); 486 *R_GEN_CONFIG = genconfig_shadow; 487 /* Must be a >120 ns delay before writing this again */ 488 } 489 return dir_g_out_bits & 0x7FFFFFFF; 490} /* setget_output */ 491 492static int 493gpio_leds_ioctl(unsigned int cmd, unsigned long arg); 494 495static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 496{ 497 unsigned long flags; 498 unsigned long val; 499 int ret = 0; 500 501 struct gpio_private *priv = file->private_data; 502 if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) 503 return -EINVAL; 504 505 switch (_IOC_NR(cmd)) { 506 case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */ 507 // read the port 508 spin_lock_irqsave(&gpio_lock, flags); 509 if (USE_PORTS(priv)) { 510 ret = *priv->port; 511 } else if (priv->minor == GPIO_MINOR_G) { 512 ret = (*R_PORT_G_DATA) & 0x7FFFFFFF; 513 } 514 spin_unlock_irqrestore(&gpio_lock, flags); 515 516 break; 517 case IO_SETBITS: 518 // set changeable bits with a 1 in arg 519 spin_lock_irqsave(&gpio_lock, flags); 520 521 if (USE_PORTS(priv)) { 522 *priv->port = *priv->shadow |= 523 ((unsigned char)arg & priv->changeable_bits); 524 } else if (priv->minor == GPIO_MINOR_G) { 525 *R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits); 526 } 527 spin_unlock_irqrestore(&gpio_lock, flags); 528 529 break; 530 case IO_CLRBITS: 531 // clear changeable bits with a 1 in arg 532 spin_lock_irqsave(&gpio_lock, flags); 533 if (USE_PORTS(priv)) { 534 *priv->port = *priv->shadow &= 535 ~((unsigned char)arg & priv->changeable_bits); 536 } else if (priv->minor == GPIO_MINOR_G) { 537 *R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits); 538 } 539 spin_unlock_irqrestore(&gpio_lock, flags); 540 break; 541 case IO_HIGHALARM: 542 // set alarm when bits with 1 in arg go high 543 spin_lock_irqsave(&gpio_lock, flags); 544 priv->highalarm |= arg; 545 gpio_some_alarms = 1; 546 spin_unlock_irqrestore(&gpio_lock, flags); 547 break; 548 case IO_LOWALARM: 549 // set alarm when bits with 1 in arg go low 550 spin_lock_irqsave(&gpio_lock, flags); 551 priv->lowalarm |= arg; 552 gpio_some_alarms = 1; 553 spin_unlock_irqrestore(&gpio_lock, flags); 554 break; 555 case IO_CLRALARM: 556 /* clear alarm for bits with 1 in arg */ 557 spin_lock_irqsave(&gpio_lock, flags); 558 priv->highalarm &= ~arg; 559 priv->lowalarm &= ~arg; 560 { 561 /* Must update gpio_some_alarms */ 562 struct gpio_private *p = alarmlist; 563 int some_alarms; 564 p = alarmlist; 565 some_alarms = 0; 566 while (p) { 567 if (p->highalarm | p->lowalarm) { 568 some_alarms = 1; 569 break; 570 } 571 p = p->next; 572 } 573 gpio_some_alarms = some_alarms; 574 } 575 spin_unlock_irqrestore(&gpio_lock, flags); 576 break; 577 case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */ 578 /* Read direction 0=input 1=output */ 579 spin_lock_irqsave(&gpio_lock, flags); 580 if (USE_PORTS(priv)) { 581 ret = *priv->dir_shadow; 582 } else if (priv->minor == GPIO_MINOR_G) { 583 /* Note: Some bits are both in and out, 584 * Those that are dual is set here as well. 585 */ 586 ret = (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF; 587 } 588 spin_unlock_irqrestore(&gpio_lock, flags); 589 break; 590 case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */ 591 /* Set direction 0=unchanged 1=input, 592 * return mask with 1=input 593 */ 594 spin_lock_irqsave(&gpio_lock, flags); 595 ret = setget_input(priv, arg) & 0x7FFFFFFF; 596 spin_unlock_irqrestore(&gpio_lock, flags); 597 break; 598 case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */ 599 /* Set direction 0=unchanged 1=output, 600 * return mask with 1=output 601 */ 602 spin_lock_irqsave(&gpio_lock, flags); 603 ret = setget_output(priv, arg) & 0x7FFFFFFF; 604 spin_unlock_irqrestore(&gpio_lock, flags); 605 break; 606 case IO_SHUTDOWN: 607 spin_lock_irqsave(&gpio_lock, flags); 608 SOFT_SHUTDOWN(); 609 spin_unlock_irqrestore(&gpio_lock, flags); 610 break; 611 case IO_GET_PWR_BT: 612 spin_lock_irqsave(&gpio_lock, flags); 613#if defined(CONFIG_ETRAX_SOFT_SHUTDOWN) 614 ret = (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT)); 615#else 616 ret = 0; 617#endif 618 spin_unlock_irqrestore(&gpio_lock, flags); 619 break; 620 case IO_CFG_WRITE_MODE: 621 spin_lock_irqsave(&gpio_lock, flags); 622 priv->clk_mask = arg & 0xFF; 623 priv->data_mask = (arg >> 8) & 0xFF; 624 priv->write_msb = (arg >> 16) & 0x01; 625 /* Check if we're allowed to change the bits and 626 * the direction is correct 627 */ 628 if (!((priv->clk_mask & priv->changeable_bits) && 629 (priv->data_mask & priv->changeable_bits) && 630 (priv->clk_mask & *priv->dir_shadow) && 631 (priv->data_mask & *priv->dir_shadow))) 632 { 633 priv->clk_mask = 0; 634 priv->data_mask = 0; 635 ret = -EPERM; 636 } 637 spin_unlock_irqrestore(&gpio_lock, flags); 638 break; 639 case IO_READ_INBITS: 640 /* *arg is result of reading the input pins */ 641 spin_lock_irqsave(&gpio_lock, flags); 642 if (USE_PORTS(priv)) { 643 val = *priv->port; 644 } else if (priv->minor == GPIO_MINOR_G) { 645 val = *R_PORT_G_DATA; 646 } 647 spin_unlock_irqrestore(&gpio_lock, flags); 648 if (copy_to_user((void __user *)arg, &val, sizeof(val))) 649 ret = -EFAULT; 650 break; 651 case IO_READ_OUTBITS: 652 /* *arg is result of reading the output shadow */ 653 spin_lock_irqsave(&gpio_lock, flags); 654 if (USE_PORTS(priv)) { 655 val = *priv->shadow; 656 } else if (priv->minor == GPIO_MINOR_G) { 657 val = port_g_data_shadow; 658 } 659 spin_unlock_irqrestore(&gpio_lock, flags); 660 if (copy_to_user((void __user *)arg, &val, sizeof(val))) 661 ret = -EFAULT; 662 break; 663 case IO_SETGET_INPUT: 664 /* bits set in *arg is set to input, 665 * *arg updated with current input pins. 666 */ 667 if (copy_from_user(&val, (void __user *)arg, sizeof(val))) 668 { 669 ret = -EFAULT; 670 break; 671 } 672 spin_lock_irqsave(&gpio_lock, flags); 673 val = setget_input(priv, val); 674 spin_unlock_irqrestore(&gpio_lock, flags); 675 if (copy_to_user((void __user *)arg, &val, sizeof(val))) 676 ret = -EFAULT; 677 break; 678 case IO_SETGET_OUTPUT: 679 /* bits set in *arg is set to output, 680 * *arg updated with current output pins. 681 */ 682 if (copy_from_user(&val, (void __user *)arg, sizeof(val))) { 683 ret = -EFAULT; 684 break; 685 } 686 spin_lock_irqsave(&gpio_lock, flags); 687 val = setget_output(priv, val); 688 spin_unlock_irqrestore(&gpio_lock, flags); 689 if (copy_to_user((void __user *)arg, &val, sizeof(val))) 690 ret = -EFAULT; 691 break; 692 default: 693 spin_lock_irqsave(&gpio_lock, flags); 694 if (priv->minor == GPIO_MINOR_LEDS) 695 ret = gpio_leds_ioctl(cmd, arg); 696 else 697 ret = -EINVAL; 698 spin_unlock_irqrestore(&gpio_lock, flags); 699 } /* switch */ 700 701 return ret; 702} 703 704static int 705gpio_leds_ioctl(unsigned int cmd, unsigned long arg) 706{ 707 unsigned char green; 708 unsigned char red; 709 710 switch (_IOC_NR(cmd)) { 711 case IO_LEDACTIVE_SET: 712 green = ((unsigned char)arg) & 1; 713 red = (((unsigned char)arg) >> 1) & 1; 714 CRIS_LED_ACTIVE_SET_G(green); 715 CRIS_LED_ACTIVE_SET_R(red); 716 break; 717 718 case IO_LED_SETBIT: 719 CRIS_LED_BIT_SET(arg); 720 break; 721 722 case IO_LED_CLRBIT: 723 CRIS_LED_BIT_CLR(arg); 724 break; 725 726 default: 727 return -EINVAL; 728 } /* switch */ 729 730 return 0; 731} 732 733static const struct file_operations gpio_fops = { 734 .owner = THIS_MODULE, 735 .poll = gpio_poll, 736 .unlocked_ioctl = gpio_ioctl, 737 .write = gpio_write, 738 .open = gpio_open, 739 .release = gpio_release, 740}; 741 742static void ioif_watcher(const unsigned int gpio_in_available, 743 const unsigned int gpio_out_available, 744 const unsigned char pa_available, 745 const unsigned char pb_available) 746{ 747 unsigned long int flags; 748 749 D(printk(KERN_DEBUG "gpio.c: ioif_watcher called\n")); 750 D(printk(KERN_DEBUG "gpio.c: G in: 0x%08x G out: 0x%08x " 751 "PA: 0x%02x PB: 0x%02x\n", 752 gpio_in_available, gpio_out_available, 753 pa_available, pb_available)); 754 755 spin_lock_irqsave(&gpio_lock, flags); 756 757 dir_g_in_bits = gpio_in_available; 758 dir_g_out_bits = gpio_out_available; 759 760 /* Initialise the dir_g_shadow etc. depending on genconfig */ 761 /* 0=input 1=output */ 762 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out)) 763 dir_g_shadow |= (1 << 0); 764 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out)) 765 dir_g_shadow |= 0x0000FF00; 766 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g16_23dir, out)) 767 dir_g_shadow |= 0x00FF0000; 768 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out)) 769 dir_g_shadow |= (1 << 24); 770 771 changeable_dir_g = changeable_dir_g_mask; 772 changeable_dir_g &= dir_g_out_bits; 773 changeable_dir_g &= dir_g_in_bits; 774 775 /* Correct the bits that can change direction */ 776 dir_g_out_bits &= ~changeable_dir_g; 777 dir_g_out_bits |= dir_g_shadow; 778 dir_g_in_bits &= ~changeable_dir_g; 779 dir_g_in_bits |= (~dir_g_shadow & changeable_dir_g); 780 781 spin_unlock_irqrestore(&gpio_lock, flags); 782 783 printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX " 784 "val: %08lX\n", 785 dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA); 786 printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n", 787 dir_g_shadow, changeable_dir_g); 788} 789 790/* main driver initialization routine, called from mem.c */ 791 792static int __init gpio_init(void) 793{ 794 int res; 795#if defined(CONFIG_ETRAX_CSP0_LEDS) 796 int i; 797#endif 798 799 res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops); 800 if (res < 0) { 801 printk(KERN_ERR "gpio: couldn't get a major number.\n"); 802 return res; 803 } 804 805 /* Clear all leds */ 806#if defined(CONFIG_ETRAX_CSP0_LEDS) || defined(CONFIG_ETRAX_PA_LEDS) || \ 807 defined(CONFIG_ETRAX_PB_LEDS) 808 CRIS_LED_NETWORK_SET(0); 809 CRIS_LED_ACTIVE_SET(0); 810 CRIS_LED_DISK_READ(0); 811 CRIS_LED_DISK_WRITE(0); 812 813#if defined(CONFIG_ETRAX_CSP0_LEDS) 814 for (i = 0; i < 32; i++) 815 CRIS_LED_BIT_SET(i); 816#endif 817 818#endif 819 /* The I/O interface allocation watcher will be called when 820 * registering it. */ 821 if (cris_io_interface_register_watcher(ioif_watcher)){ 822 printk(KERN_WARNING "gpio_init: Failed to install IO " 823 "if allocator watcher\n"); 824 } 825 826 printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001-2008 " 827 "Axis Communications AB\n"); 828 /* We call etrax_gpio_wake_up_check() from timer interrupt and 829 * from cpu_idle() in kernel/process.c 830 * The check in cpu_idle() reduces latency from ~15 ms to ~6 ms 831 * in some tests. 832 */ 833 res = request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt, 834 IRQF_SHARED | IRQF_DISABLED, "gpio poll", gpio_name); 835 if (res) { 836 printk(KERN_CRIT "err: timer0 irq for gpio\n"); 837 return res; 838 } 839 res = request_irq(PA_IRQ_NBR, gpio_interrupt, 840 IRQF_SHARED | IRQF_DISABLED, "gpio PA", gpio_name); 841 if (res) 842 printk(KERN_CRIT "err: PA irq for gpio\n"); 843 844 return res; 845} 846 847/* this makes sure that gpio_init is called during kernel boot */ 848module_init(gpio_init); 849