1/* 2 * BF561 memory map 3 * 4 * Copyright 2004-2009 Analog Devices Inc. 5 * Licensed under the GPL-2 or later. 6 */ 7 8#ifndef __BFIN_MACH_MEM_MAP_H__ 9#define __BFIN_MACH_MEM_MAP_H__ 10 11#ifndef __BFIN_MEM_MAP_H__ 12# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" 13#endif 14 15/* Async Memory Banks */ 16#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ 17#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ 18#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */ 19#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ 20#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */ 21#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ 22#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ 23#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ 24 25/* Boot ROM Memory */ 26 27#define BOOT_ROM_START 0xEF000000 28#define BOOT_ROM_LENGTH 0x800 29 30/* Level 1 Memory */ 31 32#ifdef CONFIG_BFIN_ICACHE 33#define BFIN_ICACHESIZE (16*1024) 34#else 35#define BFIN_ICACHESIZE (0*1024) 36#endif 37 38/* Memory Map for ADSP-BF561 processors */ 39 40#define COREA_L1_CODE_START 0xFFA00000 41#define COREA_L1_DATA_A_START 0xFF800000 42#define COREA_L1_DATA_B_START 0xFF900000 43#define COREB_L1_CODE_START 0xFF600000 44#define COREB_L1_DATA_A_START 0xFF400000 45#define COREB_L1_DATA_B_START 0xFF500000 46 47#define L1_CODE_START COREA_L1_CODE_START 48#define L1_DATA_A_START COREA_L1_DATA_A_START 49#define L1_DATA_B_START COREA_L1_DATA_B_START 50 51#define L1_CODE_LENGTH 0x4000 52 53#ifdef CONFIG_BFIN_DCACHE 54 55#ifdef CONFIG_BFIN_DCACHE_BANKA 56#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 57#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 58#define L1_DATA_B_LENGTH 0x8000 59#define BFIN_DCACHESIZE (16*1024) 60#define BFIN_DSUPBANKS 1 61#else 62#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 63#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 64#define L1_DATA_B_LENGTH (0x8000 - 0x4000) 65#define BFIN_DCACHESIZE (32*1024) 66#define BFIN_DSUPBANKS 2 67#endif 68 69#else 70#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 71#define L1_DATA_A_LENGTH 0x8000 72#define L1_DATA_B_LENGTH 0x8000 73#define BFIN_DCACHESIZE (0*1024) 74#define BFIN_DSUPBANKS 0 75#endif /*CONFIG_BFIN_DCACHE*/ 76 77/* 78 * If we are in SMP mode, then the cache settings of Core B will match 79 * the settings of Core A. If we aren't, then we assume Core B is not 80 * using any cache. This allows the rest of the kernel to work with 81 * the core in either mode as we are only loading user code into it and 82 * it is the user's problem to make sure they aren't doing something 83 * stupid there. 84 * 85 * Note that we treat the L1 code region as a contiguous blob to make 86 * the rest of the kernel simpler. Easier to check one region than a 87 * bunch of small ones. Again, possible misbehavior here is the fault 88 * of the user -- don't try to use memory that doesn't exist. 89 */ 90#ifdef CONFIG_SMP 91# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH 92# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH 93# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH 94#else 95# define COREB_L1_CODE_LENGTH 0x14000 96# define COREB_L1_DATA_A_LENGTH 0x8000 97# define COREB_L1_DATA_B_LENGTH 0x8000 98#endif 99 100/* Level 2 Memory */ 101#define L2_START 0xFEB00000 102#define L2_LENGTH 0x20000 103 104/* Scratch Pad Memory */ 105 106#define COREA_L1_SCRATCH_START 0xFFB00000 107#define COREB_L1_SCRATCH_START 0xFF700000 108 109#ifdef __ASSEMBLY__ 110 111/* 112 * The following macros both return the address of the PDA for the 113 * current core. 114 * 115 * In its first safe (and hairy) form, the macro neither clobbers any 116 * register aside of the output Preg, nor uses the stack, since it 117 * could be called with an invalid stack pointer, or the current stack 118 * space being uncovered by any CPLB (e.g. early exception handling). 119 * 120 * The constraints on the second form are a bit relaxed, and the code 121 * is allowed to use the specified Dreg for determining the PDA 122 * address to be returned into Preg. 123 */ 124#ifdef CONFIG_SMP 125#define GET_PDA_SAFE(preg) \ 126 preg.l = lo(DSPID); \ 127 preg.h = hi(DSPID); \ 128 preg = [preg]; \ 129 preg = preg << 2; \ 130 preg = preg << 2; \ 131 preg = preg << 2; \ 132 preg = preg << 2; \ 133 preg = preg << 2; \ 134 preg = preg << 2; \ 135 preg = preg << 2; \ 136 preg = preg << 2; \ 137 preg = preg << 2; \ 138 preg = preg << 2; \ 139 preg = preg << 2; \ 140 preg = preg << 2; \ 141 if cc jump 2f; \ 142 cc = preg == 0x0; \ 143 preg.l = _cpu_pda; \ 144 preg.h = _cpu_pda; \ 145 if !cc jump 3f; \ 1461: \ 147 /* preg = 0x0; */ \ 148 cc = !cc; /* restore cc to 0 */ \ 149 jump 4f; \ 1502: \ 151 cc = preg == 0x0; \ 152 preg.l = _cpu_pda; \ 153 preg.h = _cpu_pda; \ 154 if cc jump 4f; \ 155 /* preg = 0x1000000; */ \ 156 cc = !cc; /* restore cc to 1 */ \ 1573: \ 158 preg = [preg]; \ 1594: 160 161#define GET_PDA(preg, dreg) \ 162 preg.l = lo(DSPID); \ 163 preg.h = hi(DSPID); \ 164 dreg = [preg]; \ 165 preg.l = _cpu_pda; \ 166 preg.h = _cpu_pda; \ 167 cc = bittst(dreg, 0); \ 168 if !cc jump 1f; \ 169 preg = [preg]; \ 1701: \ 171 172#define GET_CPUID(preg, dreg) \ 173 preg.l = lo(DSPID); \ 174 preg.h = hi(DSPID); \ 175 dreg = [preg]; \ 176 dreg = ROT dreg BY -1; \ 177 dreg = CC; 178 179static inline unsigned long get_l1_scratch_start_cpu(int cpu) 180{ 181 return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; 182} 183static inline unsigned long get_l1_code_start_cpu(int cpu) 184{ 185 return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START; 186} 187static inline unsigned long get_l1_data_a_start_cpu(int cpu) 188{ 189 return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START; 190} 191static inline unsigned long get_l1_data_b_start_cpu(int cpu) 192{ 193 return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START; 194} 195 196static inline unsigned long get_l1_scratch_start(void) 197{ 198 return get_l1_scratch_start_cpu(blackfin_core_id()); 199} 200static inline unsigned long get_l1_code_start(void) 201{ 202 return get_l1_code_start_cpu(blackfin_core_id()); 203} 204static inline unsigned long get_l1_data_a_start(void) 205{ 206 return get_l1_data_a_start_cpu(blackfin_core_id()); 207} 208static inline unsigned long get_l1_data_b_start(void) 209{ 210 return get_l1_data_b_start_cpu(blackfin_core_id()); 211} 212 213#endif /* CONFIG_SMP */ 214 215#endif /* __ASSEMBLY__ */ 216 217#endif 218