1/* 2 * Copyright 2007-2008 Analog Devices Inc. 3 * 4 * Licensed under the ADI BSD license or the GPL-2 (or later) 5 */ 6 7#ifndef _DEF_BF542_H 8#define _DEF_BF542_H 9 10/* Include all Core registers and bit definitions */ 11#include <asm/def_LPBlackfin.h> 12 13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */ 14 15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 16#include "defBF54x_base.h" 17 18/* The following are the #defines needed by ADSP-BF542 that are not in the common header */ 19 20/* ATAPI Registers */ 21 22#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ 23#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ 24#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ 25#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ 26#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ 27#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ 28#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ 29#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ 30#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ 31#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ 32#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ 33#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ 34#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ 35#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ 36#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ 37#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ 38#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ 39#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ 40#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ 41#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ 42#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ 43#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ 44#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ 45#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ 46#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ 47 48/* SDH Registers */ 49 50#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ 51#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ 52#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ 53#define SDH_COMMAND 0xffc0390c /* SDH Command */ 54#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ 55#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ 56#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ 57#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ 58#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ 59#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ 60#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ 61#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ 62#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ 63#define SDH_STATUS 0xffc03934 /* SDH Status */ 64#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ 65#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ 66#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ 67#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ 68#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ 69#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ 70#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ 71#define SDH_CFG 0xffc039c8 /* SDH Configuration */ 72#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ 73#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ 74#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ 75#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ 76#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ 77#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ 78#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ 79#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ 80#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ 81 82/* USB Control Registers */ 83 84#define USB_FADDR 0xffc03c00 /* Function address register */ 85#define USB_POWER 0xffc03c04 /* Power management register */ 86#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ 87#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ 88#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ 89#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ 90#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ 91#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ 92#define USB_FRAME 0xffc03c20 /* USB frame number */ 93#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ 94#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ 95#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ 96#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ 97 98/* USB Packet Control Registers */ 99 100#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ 101#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ 102#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ 103#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ 104#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ 105#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ 106#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ 107#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ 108#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ 109#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ 110#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ 111#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ 112#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ 113 114/* USB Endpoint FIFO Registers */ 115 116#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ 117#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ 118#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ 119#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ 120#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ 121#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ 122#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ 123#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ 124 125/* USB OTG Control Registers */ 126 127#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ 128#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ 129#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ 130 131/* USB Phy Control Registers */ 132 133#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ 134#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ 135#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ 136#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ 137#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ 138 139/* (APHY_CNTRL is for ADI usage only) */ 140 141#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ 142 143/* (APHY_CALIB is for ADI usage only) */ 144 145#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ 146#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ 147 148/* (PHY_TEST is for ADI usage only) */ 149 150#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ 151#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ 152#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ 153 154/* USB Endpoint 0 Control Registers */ 155 156#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ 157#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ 158#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ 159#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ 160#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ 161#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ 162#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ 163#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ 164#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ 165 166/* USB Endpoint 1 Control Registers */ 167 168#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ 169#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ 170#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ 171#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ 172#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ 173#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ 174#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ 175#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ 176#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ 177#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ 178 179/* USB Endpoint 2 Control Registers */ 180 181#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ 182#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ 183#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ 184#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ 185#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ 186#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ 187#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ 188#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ 189#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ 190#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ 191 192/* USB Endpoint 3 Control Registers */ 193 194#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ 195#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ 196#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ 197#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ 198#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ 199#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ 200#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ 201#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ 202#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ 203#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ 204 205/* USB Endpoint 4 Control Registers */ 206 207#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ 208#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ 209#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ 210#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ 211#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ 212#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ 213#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ 214#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ 215#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ 216#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ 217 218/* USB Endpoint 5 Control Registers */ 219 220#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ 221#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ 222#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ 223#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ 224#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ 225#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ 226#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ 227#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ 228#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ 229#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ 230 231/* USB Endpoint 6 Control Registers */ 232 233#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ 234#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ 235#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ 236#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ 237#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ 238#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ 239#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ 240#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ 241#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ 242#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ 243 244/* USB Endpoint 7 Control Registers */ 245 246#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ 247#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ 248#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ 249#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ 250#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ 251#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ 252#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ 253#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ 254#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ 255#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ 256#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ 257#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ 258 259/* USB Channel 0 Config Registers */ 260 261#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ 262#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ 263#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ 264#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ 265#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ 266 267/* USB Channel 1 Config Registers */ 268 269#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ 270#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ 271#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ 272#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ 273#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ 274 275/* USB Channel 2 Config Registers */ 276 277#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ 278#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ 279#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ 280#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ 281#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ 282 283/* USB Channel 3 Config Registers */ 284 285#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ 286#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ 287#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ 288#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ 289#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ 290 291/* USB Channel 4 Config Registers */ 292 293#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ 294#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ 295#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ 296#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ 297#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ 298 299/* USB Channel 5 Config Registers */ 300 301#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ 302#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ 303#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ 304#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ 305#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ 306 307/* USB Channel 6 Config Registers */ 308 309#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ 310#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ 311#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ 312#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ 313#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ 314 315/* USB Channel 7 Config Registers */ 316 317#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ 318#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ 319#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ 320#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ 321#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ 322 323/* Keypad Registers */ 324 325#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ 326#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ 327#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ 328#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ 329#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ 330#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ 331 332 333/* ********************************************************** */ 334/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ 335/* and MULTI BIT READ MACROS */ 336/* ********************************************************** */ 337 338/* Bit masks for KPAD_CTL */ 339 340#define KPAD_EN 0x1 /* Keypad Enable */ 341#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ 342#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ 343#define KPAD_COLEN 0xe000 /* Column Enable Width */ 344 345/* Bit masks for KPAD_PRESCALE */ 346 347#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ 348 349/* Bit masks for KPAD_MSEL */ 350 351#define DBON_SCALE 0xff /* Debounce Scale Value */ 352#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ 353 354/* Bit masks for KPAD_ROWCOL */ 355 356#define KPAD_ROW 0xff /* Rows Pressed */ 357#define KPAD_COL 0xff00 /* Columns Pressed */ 358 359/* Bit masks for KPAD_STAT */ 360 361#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ 362#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ 363#define KPAD_PRESSED 0x8 /* Key press current status */ 364 365/* Bit masks for KPAD_SOFTEVAL */ 366 367#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ 368 369/* Bit masks for ATAPI_CONTROL */ 370 371#define PIO_START 0x1 /* Start PIO/Reg Op */ 372#define MULTI_START 0x2 /* Start Multi-DMA Op */ 373#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ 374#define XFER_DIR 0x8 /* Transfer Direction */ 375#define IORDY_EN 0x10 /* IORDY Enable */ 376#define FIFO_FLUSH 0x20 /* Flush FIFOs */ 377#define SOFT_RST 0x40 /* Soft Reset */ 378#define DEV_RST 0x80 /* Device Reset */ 379#define TFRCNT_RST 0x100 /* Trans Count Reset */ 380#define END_ON_TERM 0x200 /* End/Terminate Select */ 381#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ 382#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ 383 384/* Bit masks for ATAPI_STATUS */ 385 386#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ 387#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ 388#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ 389#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ 390 391/* Bit masks for ATAPI_DEV_ADDR */ 392 393#define DEV_ADDR 0x1f /* Device Address */ 394 395/* Bit masks for ATAPI_INT_MASK */ 396 397#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ 398#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ 399#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ 400#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ 401#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ 402#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ 403#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ 404#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ 405#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ 406 407/* Bit masks for ATAPI_INT_STATUS */ 408 409#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ 410#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ 411#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ 412#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ 413#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ 414#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ 415#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ 416#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ 417#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ 418 419/* Bit masks for ATAPI_LINE_STATUS */ 420 421#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ 422#define ATAPI_DASP 0x2 /* Device dasp to host line status */ 423#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ 424#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ 425#define ATAPI_ADDR 0x70 /* ATAPI address line status */ 426#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ 427#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ 428#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ 429#define ATAPI_DIORN 0x400 /* ATAPI read line status */ 430#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ 431 432/* Bit masks for ATAPI_SM_STATE */ 433 434#define PIO_CSTATE 0xf /* PIO mode state machine current state */ 435#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ 436#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ 437#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ 438 439/* Bit masks for ATAPI_TERMINATE */ 440 441#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ 442 443/* Bit masks for ATAPI_REG_TIM_0 */ 444 445#define T2_REG 0xff /* End of cycle time for register access transfers */ 446#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ 447 448/* Bit masks for ATAPI_PIO_TIM_0 */ 449 450#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ 451#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ 452#define T4_REG 0xf000 /* DIOW data hold */ 453 454/* Bit masks for ATAPI_PIO_TIM_1 */ 455 456#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ 457 458/* Bit masks for ATAPI_MULTI_TIM_0 */ 459 460#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ 461#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ 462 463/* Bit masks for ATAPI_MULTI_TIM_1 */ 464 465#define TKW 0xff /* Selects DIOW negated pulsewidth */ 466#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ 467 468/* Bit masks for ATAPI_MULTI_TIM_2 */ 469 470#define TH 0xff /* Selects DIOW data hold */ 471#define TEOC 0xff00 /* Selects end of cycle for DMA */ 472 473/* Bit masks for ATAPI_ULTRA_TIM_0 */ 474 475#define TACK 0xff /* Selects setup and hold times for TACK */ 476#define TENV 0xff00 /* Selects envelope time */ 477 478/* Bit masks for ATAPI_ULTRA_TIM_1 */ 479 480#define TDVS 0xff /* Selects data valid setup time */ 481#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ 482 483/* Bit masks for ATAPI_ULTRA_TIM_2 */ 484 485#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ 486#define TMLI 0xff00 /* Selects interlock time */ 487 488/* Bit masks for ATAPI_ULTRA_TIM_3 */ 489 490#define TZAH 0xff /* Selects minimum delay required for output */ 491#define READY_PAUSE 0xff00 /* Selects ready to pause */ 492 493/* Bit masks for USB_FADDR */ 494 495#define FUNCTION_ADDRESS 0x7f /* Function address */ 496 497/* Bit masks for USB_POWER */ 498 499#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ 500#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ 501#define RESUME_MODE 0x4 /* DMA Mode */ 502#define RESET 0x8 /* Reset indicator */ 503#define HS_MODE 0x10 /* High Speed mode indicator */ 504#define HS_ENABLE 0x20 /* high Speed Enable */ 505#define SOFT_CONN 0x40 /* Soft connect */ 506#define ISO_UPDATE 0x80 /* Isochronous update */ 507 508/* Bit masks for USB_INTRTX */ 509 510#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ 511#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ 512#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ 513#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ 514#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ 515#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ 516#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ 517#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ 518 519/* Bit masks for USB_INTRRX */ 520 521#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ 522#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ 523#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ 524#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ 525#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ 526#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ 527#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ 528 529/* Bit masks for USB_INTRTXE */ 530 531#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ 532#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ 533#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ 534#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ 535#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ 536#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ 537#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ 538#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ 539 540/* Bit masks for USB_INTRRXE */ 541 542#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ 543#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ 544#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ 545#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ 546#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ 547#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ 548#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ 549 550/* Bit masks for USB_INTRUSB */ 551 552#define SUSPEND_B 0x1 /* Suspend indicator */ 553#define RESUME_B 0x2 /* Resume indicator */ 554#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ 555#define SOF_B 0x8 /* Start of frame */ 556#define CONN_B 0x10 /* Connection indicator */ 557#define DISCON_B 0x20 /* Disconnect indicator */ 558#define SESSION_REQ_B 0x40 /* Session Request */ 559#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ 560 561/* Bit masks for USB_INTRUSBE */ 562 563#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ 564#define RESUME_BE 0x2 /* Resume indicator int enable */ 565#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ 566#define SOF_BE 0x8 /* Start of frame int enable */ 567#define CONN_BE 0x10 /* Connection indicator int enable */ 568#define DISCON_BE 0x20 /* Disconnect indicator int enable */ 569#define SESSION_REQ_BE 0x40 /* Session Request int enable */ 570#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ 571 572/* Bit masks for USB_FRAME */ 573 574#define FRAME_NUMBER 0x7ff /* Frame number */ 575 576/* Bit masks for USB_INDEX */ 577 578#define SELECTED_ENDPOINT 0xf /* selected endpoint */ 579 580/* Bit masks for USB_GLOBAL_CTL */ 581 582#define GLOBAL_ENA 0x1 /* enables USB module */ 583#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ 584#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ 585#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ 586#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ 587#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ 588#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ 589#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ 590#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ 591#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ 592#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ 593#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ 594#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ 595#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ 596#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ 597 598/* Bit masks for USB_OTG_DEV_CTL */ 599 600#define SESSION 0x1 /* session indicator */ 601#define HOST_REQ 0x2 /* Host negotiation request */ 602#define HOST_MODE 0x4 /* indicates USBDRC is a host */ 603#define VBUS0 0x8 /* Vbus level indicator[0] */ 604#define VBUS1 0x10 /* Vbus level indicator[1] */ 605#define LSDEV 0x20 /* Low-speed indicator */ 606#define FSDEV 0x40 /* Full or High-speed indicator */ 607#define B_DEVICE 0x80 /* A' or 'B' device indicator */ 608 609/* Bit masks for USB_OTG_VBUS_IRQ */ 610 611#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ 612#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ 613#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ 614#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ 615#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ 616#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ 617 618/* Bit masks for USB_OTG_VBUS_MASK */ 619 620#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ 621#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ 622#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ 623#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ 624#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ 625#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ 626 627/* Bit masks for USB_CSR0 */ 628 629#define RXPKTRDY 0x1 /* data packet receive indicator */ 630#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ 631#define STALL_SENT 0x4 /* STALL handshake sent */ 632#define DATAEND 0x8 /* Data end indicator */ 633#define SETUPEND 0x10 /* Setup end */ 634#define SENDSTALL 0x20 /* Send STALL handshake */ 635#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ 636#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ 637#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ 638#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ 639#define SETUPPKT_H 0x8 /* send Setup token host mode */ 640#define ERROR_H 0x10 /* timeout error indicator host mode */ 641#define REQPKT_H 0x20 /* Request an IN transaction host mode */ 642#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ 643#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ 644 645/* Bit masks for USB_COUNT0 */ 646 647#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ 648 649/* Bit masks for USB_NAKLIMIT0 */ 650 651#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ 652 653/* Bit masks for USB_TX_MAX_PACKET */ 654 655#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ 656 657/* Bit masks for USB_RX_MAX_PACKET */ 658 659#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ 660 661/* Bit masks for USB_TXCSR */ 662 663#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ 664#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ 665#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ 666#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ 667#define STALL_SEND_T 0x10 /* issue a Stall handshake */ 668#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ 669#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ 670#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ 671#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ 672#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ 673#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ 674#define ISO_T 0x4000 /* enable Isochronous transfers */ 675#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ 676#define ERROR_TH 0x4 /* error condition host mode */ 677#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ 678#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ 679 680/* Bit masks for USB_TXCOUNT */ 681 682#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ 683 684/* Bit masks for USB_RXCSR */ 685 686#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ 687#define FIFO_FULL_R 0x2 /* FIFO not empty */ 688#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ 689#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ 690#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ 691#define STALL_SEND_R 0x20 /* issue a Stall handshake */ 692#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ 693#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ 694#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ 695#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ 696#define DISNYET_R 0x1000 /* disable Nyet handshakes */ 697#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ 698#define ISO_R 0x4000 /* enable Isochronous transfers */ 699#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ 700#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ 701#define REQPKT_RH 0x20 /* request an IN transaction host mode */ 702#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ 703#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ 704#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ 705#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ 706 707/* Bit masks for USB_RXCOUNT */ 708 709#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ 710 711/* Bit masks for USB_TXTYPE */ 712 713#define TARGET_EP_NO_T 0xf /* EP number */ 714#define PROTOCOL_T 0xc /* transfer type */ 715 716/* Bit masks for USB_TXINTERVAL */ 717 718#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ 719 720/* Bit masks for USB_RXTYPE */ 721 722#define TARGET_EP_NO_R 0xf /* EP number */ 723#define PROTOCOL_R 0xc /* transfer type */ 724 725/* Bit masks for USB_RXINTERVAL */ 726 727#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ 728 729/* Bit masks for USB_DMA_INTERRUPT */ 730 731#define DMA0_INT 0x1 /* DMA0 pending interrupt */ 732#define DMA1_INT 0x2 /* DMA1 pending interrupt */ 733#define DMA2_INT 0x4 /* DMA2 pending interrupt */ 734#define DMA3_INT 0x8 /* DMA3 pending interrupt */ 735#define DMA4_INT 0x10 /* DMA4 pending interrupt */ 736#define DMA5_INT 0x20 /* DMA5 pending interrupt */ 737#define DMA6_INT 0x40 /* DMA6 pending interrupt */ 738#define DMA7_INT 0x80 /* DMA7 pending interrupt */ 739 740/* Bit masks for USB_DMAxCONTROL */ 741 742#define DMA_ENA 0x1 /* DMA enable */ 743#define DIRECTION 0x2 /* direction of DMA transfer */ 744#define MODE 0x4 /* DMA Bus error */ 745#define INT_ENA 0x8 /* Interrupt enable */ 746#define EPNUM 0xf0 /* EP number */ 747#define BUSERROR 0x100 /* DMA Bus error */ 748 749/* Bit masks for USB_DMAxADDRHIGH */ 750 751#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ 752 753/* Bit masks for USB_DMAxADDRLOW */ 754 755#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ 756 757/* Bit masks for USB_DMAxCOUNTHIGH */ 758 759#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ 760 761/* Bit masks for USB_DMAxCOUNTLOW */ 762 763#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ 764 765 766/* ******************************************* */ 767/* MULTI BIT MACRO ENUMERATIONS */ 768/* ******************************************* */ 769 770 771#endif /* _DEF_BF542_H */ 772