1/* 2 * Copyright 2007-2008 Analog Devices Inc. 3 * 4 * Licensed under the GPL-2 or later 5 */ 6 7#ifndef _BF527_IRQ_H_ 8#define _BF527_IRQ_H_ 9 10/* 11 * Interrupt source definitions 12 Event Source Core Event Name 13 Core Emulation ** 14 Events (highest priority) EMU 0 15 Reset RST 1 16 NMI NMI 2 17 Exception EVX 3 18 Reserved -- 4 19 Hardware Error IVHW 5 20 Core Timer IVTMR 6 * 21 22 ..... 23 24 Software Interrupt 1 IVG14 31 25 Software Interrupt 2 -- 26 (lowest priority) IVG15 32 * 27*/ 28 29#define NR_PERI_INTS (2 * 32) 30 31/* The ABSTRACT IRQ definitions */ 32/** the first seven of the following are fixed, the rest you change if you need to **/ 33#define IRQ_EMU 0 /* Emulation */ 34#define IRQ_RST 1 /* reset */ 35#define IRQ_NMI 2 /* Non Maskable */ 36#define IRQ_EVX 3 /* Exception */ 37#define IRQ_UNUSED 4 /* - unused interrupt */ 38#define IRQ_HWERR 5 /* Hardware Error */ 39#define IRQ_CORETMR 6 /* Core timer */ 40 41#define BFIN_IRQ(x) ((x) + 7) 42 43#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 44#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 45#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */ 46#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */ 47#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */ 48#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */ 49#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */ 50#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */ 51#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */ 52#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */ 53#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ 54#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ 55#define IRQ_RTC BFIN_IRQ(14) /* RTC */ 56#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */ 57#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ 58#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ 59#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */ 60#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ 61#define IRQ_TWI BFIN_IRQ(20) /* TWI */ 62#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */ 63#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ 64#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ 65#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ 66#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ 67#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ 68#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ 69#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */ 70#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ 71#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 72#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 73#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ 74#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */ 75#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */ 76#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */ 77#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */ 78#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */ 79#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */ 80#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */ 81#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */ 82#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ 83#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ 84#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ 85#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */ 86#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */ 87#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */ 88#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */ 89#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */ 90#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */ 91#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */ 92#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */ 93#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */ 94#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */ 95#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */ 96#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */ 97#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */ 98 99#define SYS_IRQS BFIN_IRQ(63) /* 70 */ 100 101#define IRQ_PF0 71 102#define IRQ_PF1 72 103#define IRQ_PF2 73 104#define IRQ_PF3 74 105#define IRQ_PF4 75 106#define IRQ_PF5 76 107#define IRQ_PF6 77 108#define IRQ_PF7 78 109#define IRQ_PF8 79 110#define IRQ_PF9 80 111#define IRQ_PF10 81 112#define IRQ_PF11 82 113#define IRQ_PF12 83 114#define IRQ_PF13 84 115#define IRQ_PF14 85 116#define IRQ_PF15 86 117 118#define IRQ_PG0 87 119#define IRQ_PG1 88 120#define IRQ_PG2 89 121#define IRQ_PG3 90 122#define IRQ_PG4 91 123#define IRQ_PG5 92 124#define IRQ_PG6 93 125#define IRQ_PG7 94 126#define IRQ_PG8 95 127#define IRQ_PG9 96 128#define IRQ_PG10 97 129#define IRQ_PG11 98 130#define IRQ_PG12 99 131#define IRQ_PG13 100 132#define IRQ_PG14 101 133#define IRQ_PG15 102 134 135#define IRQ_PH0 103 136#define IRQ_PH1 104 137#define IRQ_PH2 105 138#define IRQ_PH3 106 139#define IRQ_PH4 107 140#define IRQ_PH5 108 141#define IRQ_PH6 109 142#define IRQ_PH7 110 143#define IRQ_PH8 111 144#define IRQ_PH9 112 145#define IRQ_PH10 113 146#define IRQ_PH11 114 147#define IRQ_PH12 115 148#define IRQ_PH13 116 149#define IRQ_PH14 117 150#define IRQ_PH15 118 151 152#define GPIO_IRQ_BASE IRQ_PF0 153 154#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */ 155#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */ 156#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */ 157#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */ 158#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */ 159#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */ 160#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */ 161#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ 162 163#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 164#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) 165 166#define IVG7 7 167#define IVG8 8 168#define IVG9 9 169#define IVG10 10 170#define IVG11 11 171#define IVG12 12 172#define IVG13 13 173#define IVG14 14 174#define IVG15 15 175 176/* IAR0 BIT FIELDS */ 177#define IRQ_PLL_WAKEUP_POS 0 178#define IRQ_DMA0_ERROR_POS 4 179#define IRQ_DMAR0_BLK_POS 8 180#define IRQ_DMAR1_BLK_POS 12 181#define IRQ_DMAR0_OVR_POS 16 182#define IRQ_DMAR1_OVR_POS 20 183#define IRQ_PPI_ERROR_POS 24 184#define IRQ_MAC_ERROR_POS 28 185 186/* IAR1 BIT FIELDS */ 187#define IRQ_SPORT0_ERROR_POS 0 188#define IRQ_SPORT1_ERROR_POS 4 189#define IRQ_UART0_ERROR_POS 16 190#define IRQ_UART1_ERROR_POS 20 191#define IRQ_RTC_POS 24 192#define IRQ_PPI_POS 28 193 194/* IAR2 BIT FIELDS */ 195#define IRQ_SPORT0_RX_POS 0 196#define IRQ_SPORT0_TX_POS 4 197#define IRQ_SPORT1_RX_POS 8 198#define IRQ_SPORT1_TX_POS 12 199#define IRQ_TWI_POS 16 200#define IRQ_SPI_POS 20 201#define IRQ_UART0_RX_POS 24 202#define IRQ_UART0_TX_POS 28 203 204/* IAR3 BIT FIELDS */ 205#define IRQ_UART1_RX_POS 0 206#define IRQ_UART1_TX_POS 4 207#define IRQ_OPTSEC_POS 8 208#define IRQ_CNT_POS 12 209#define IRQ_MAC_RX_POS 16 210#define IRQ_PORTH_INTA_POS 20 211#define IRQ_MAC_TX_POS 24 212#define IRQ_PORTH_INTB_POS 28 213 214/* IAR4 BIT FIELDS */ 215#define IRQ_TIMER0_POS 0 216#define IRQ_TIMER1_POS 4 217#define IRQ_TIMER2_POS 8 218#define IRQ_TIMER3_POS 12 219#define IRQ_TIMER4_POS 16 220#define IRQ_TIMER5_POS 20 221#define IRQ_TIMER6_POS 24 222#define IRQ_TIMER7_POS 28 223 224/* IAR5 BIT FIELDS */ 225#define IRQ_PORTG_INTA_POS 0 226#define IRQ_PORTG_INTB_POS 4 227#define IRQ_MEM_DMA0_POS 8 228#define IRQ_MEM_DMA1_POS 12 229#define IRQ_WATCH_POS 16 230#define IRQ_PORTF_INTA_POS 20 231#define IRQ_PORTF_INTB_POS 24 232#define IRQ_SPI_ERROR_POS 28 233 234/* IAR6 BIT FIELDS */ 235#define IRQ_NFC_ERROR_POS 0 236#define IRQ_HDMA_ERROR_POS 4 237#define IRQ_HDMA_POS 8 238#define IRQ_USB_EINT_POS 12 239#define IRQ_USB_INT0_POS 16 240#define IRQ_USB_INT1_POS 20 241#define IRQ_USB_INT2_POS 24 242#define IRQ_USB_DMA_POS 28 243 244#endif /* _BF527_IRQ_H_ */ 245