1/* provide some functions which dump the trace buffer, in a nice way for people 2 * to read it, and understand what is going on 3 * 4 * Copyright 2004-2010 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later 7 */ 8 9#include <linux/kernel.h> 10#include <linux/hardirq.h> 11#include <linux/thread_info.h> 12#include <linux/mm.h> 13#include <linux/uaccess.h> 14#include <linux/module.h> 15#include <linux/kallsyms.h> 16#include <linux/err.h> 17#include <linux/fs.h> 18#include <asm/dma.h> 19#include <asm/trace.h> 20#include <asm/fixed_code.h> 21#include <asm/traps.h> 22#include <asm/irq_handler.h> 23 24void decode_address(char *buf, unsigned long address) 25{ 26 struct task_struct *p; 27 struct mm_struct *mm; 28 unsigned long flags, offset; 29 unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); 30 struct rb_node *n; 31 32#ifdef CONFIG_KALLSYMS 33 unsigned long symsize; 34 const char *symname; 35 char *modname; 36 char *delim = ":"; 37 char namebuf[128]; 38#endif 39 40 buf += sprintf(buf, "<0x%08lx> ", address); 41 42#ifdef CONFIG_KALLSYMS 43 /* look up the address and see if we are in kernel space */ 44 symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf); 45 46 if (symname) { 47 /* yeah! kernel space! */ 48 if (!modname) 49 modname = delim = ""; 50 sprintf(buf, "{ %s%s%s%s + 0x%lx }", 51 delim, modname, delim, symname, 52 (unsigned long)offset); 53 return; 54 } 55#endif 56 57 if (address >= FIXED_CODE_START && address < FIXED_CODE_END) { 58 /* Problem in fixed code section? */ 59 strcat(buf, "/* Maybe fixed code section */"); 60 return; 61 62 } else if (address < CONFIG_BOOT_LOAD) { 63 /* Problem somewhere before the kernel start address */ 64 strcat(buf, "/* Maybe null pointer? */"); 65 return; 66 67 } else if (address >= COREMMR_BASE) { 68 strcat(buf, "/* core mmrs */"); 69 return; 70 71 } else if (address >= SYSMMR_BASE) { 72 strcat(buf, "/* system mmrs */"); 73 return; 74 75 } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) { 76 strcat(buf, "/* on-chip L1 ROM */"); 77 return; 78 79 } else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) { 80 strcat(buf, "/* on-chip scratchpad */"); 81 return; 82 83 } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) { 84 strcat(buf, "/* unconnected memory */"); 85 return; 86 87 } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) { 88 strcat(buf, "/* reserved memory */"); 89 return; 90 91 } else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) { 92 strcat(buf, "/* on-chip Data Bank A */"); 93 return; 94 95 } else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) { 96 strcat(buf, "/* on-chip Data Bank B */"); 97 return; 98 } 99 100 /* 101 * Don't walk any of the vmas if we are oopsing, it has been known 102 * to cause problems - corrupt vmas (kernel crashes) cause double faults 103 */ 104 if (oops_in_progress) { 105 strcat(buf, "/* kernel dynamic memory (maybe user-space) */"); 106 return; 107 } 108 109 /* looks like we're off in user-land, so let's walk all the 110 * mappings of all our processes and see if we can't be a whee 111 * bit more specific 112 */ 113 write_lock_irqsave(&tasklist_lock, flags); 114 for_each_process(p) { 115 mm = (in_atomic ? p->mm : get_task_mm(p)); 116 if (!mm) 117 continue; 118 119 if (!down_read_trylock(&mm->mmap_sem)) { 120 if (!in_atomic) 121 mmput(mm); 122 continue; 123 } 124 125 for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) { 126 struct vm_area_struct *vma; 127 128 vma = rb_entry(n, struct vm_area_struct, vm_rb); 129 130 if (address >= vma->vm_start && address < vma->vm_end) { 131 char _tmpbuf[256]; 132 char *name = p->comm; 133 struct file *file = vma->vm_file; 134 135 if (file) { 136 char *d_name = d_path(&file->f_path, _tmpbuf, 137 sizeof(_tmpbuf)); 138 if (!IS_ERR(d_name)) 139 name = d_name; 140 } 141 142 /* FLAT does not have its text aligned to the start of 143 * the map while FDPIC ELF does ... 144 */ 145 146 /* before we can check flat/fdpic, we need to 147 * make sure current is valid 148 */ 149 if ((unsigned long)current >= FIXED_CODE_START && 150 !((unsigned long)current & 0x3)) { 151 if (current->mm && 152 (address > current->mm->start_code) && 153 (address < current->mm->end_code)) 154 offset = address - current->mm->start_code; 155 else 156 offset = (address - vma->vm_start) + 157 (vma->vm_pgoff << PAGE_SHIFT); 158 159 sprintf(buf, "[ %s + 0x%lx ]", name, offset); 160 } else 161 sprintf(buf, "[ %s vma:0x%lx-0x%lx]", 162 name, vma->vm_start, vma->vm_end); 163 164 up_read(&mm->mmap_sem); 165 if (!in_atomic) 166 mmput(mm); 167 168 if (buf[0] == '\0') 169 sprintf(buf, "[ %s ] dynamic memory", name); 170 171 goto done; 172 } 173 } 174 175 up_read(&mm->mmap_sem); 176 if (!in_atomic) 177 mmput(mm); 178 } 179 180 /* 181 * we were unable to find this address anywhere, 182 * or some MMs were skipped because they were in use. 183 */ 184 sprintf(buf, "/* kernel dynamic memory */"); 185 186done: 187 write_unlock_irqrestore(&tasklist_lock, flags); 188} 189 190#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1) 191 192/* 193 * Similar to get_user, do some address checking, then dereference 194 * Return true on success, false on bad address 195 */ 196bool get_mem16(unsigned short *val, unsigned short *address) 197{ 198 unsigned long addr = (unsigned long)address; 199 200 /* Check for odd addresses */ 201 if (addr & 0x1) 202 return false; 203 204 switch (bfin_mem_access_type(addr, 2)) { 205 case BFIN_MEM_ACCESS_CORE: 206 case BFIN_MEM_ACCESS_CORE_ONLY: 207 *val = *address; 208 return true; 209 case BFIN_MEM_ACCESS_DMA: 210 dma_memcpy(val, address, 2); 211 return true; 212 case BFIN_MEM_ACCESS_ITEST: 213 isram_memcpy(val, address, 2); 214 return true; 215 default: /* invalid access */ 216 return false; 217 } 218} 219 220bool get_instruction(unsigned int *val, unsigned short *address) 221{ 222 unsigned long addr = (unsigned long)address; 223 unsigned short opcode0, opcode1; 224 225 /* Check for odd addresses */ 226 if (addr & 0x1) 227 return false; 228 229 /* MMR region will never have instructions */ 230 if (addr >= SYSMMR_BASE) 231 return false; 232 233 /* Scratchpad will never have instructions */ 234 if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH) 235 return false; 236 237 /* Data banks will never have instructions */ 238 if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START) 239 return false; 240 241 if (!get_mem16(&opcode0, address)) 242 return false; 243 244 /* was this a 32-bit instruction? If so, get the next 16 bits */ 245 if ((opcode0 & 0xc000) == 0xc000) { 246 if (!get_mem16(&opcode1, address + 1)) 247 return false; 248 *val = (opcode0 << 16) + opcode1; 249 } else 250 *val = opcode0; 251 252 return true; 253} 254 255#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON) 256/* 257 * decode the instruction if we are printing out the trace, as it 258 * makes things easier to follow, without running it through objdump 259 * Decode the change of flow, and the common load/store instructions 260 * which are the main cause for faults, and discontinuities in the trace 261 * buffer. 262 */ 263 264#define ProgCtrl_opcode 0x0000 265#define ProgCtrl_poprnd_bits 0 266#define ProgCtrl_poprnd_mask 0xf 267#define ProgCtrl_prgfunc_bits 4 268#define ProgCtrl_prgfunc_mask 0xf 269#define ProgCtrl_code_bits 8 270#define ProgCtrl_code_mask 0xff 271 272static void decode_ProgCtrl_0(unsigned int opcode) 273{ 274 int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask); 275 int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask); 276 277 if (prgfunc == 0 && poprnd == 0) 278 pr_cont("NOP"); 279 else if (prgfunc == 1 && poprnd == 0) 280 pr_cont("RTS"); 281 else if (prgfunc == 1 && poprnd == 1) 282 pr_cont("RTI"); 283 else if (prgfunc == 1 && poprnd == 2) 284 pr_cont("RTX"); 285 else if (prgfunc == 1 && poprnd == 3) 286 pr_cont("RTN"); 287 else if (prgfunc == 1 && poprnd == 4) 288 pr_cont("RTE"); 289 else if (prgfunc == 2 && poprnd == 0) 290 pr_cont("IDLE"); 291 else if (prgfunc == 2 && poprnd == 3) 292 pr_cont("CSYNC"); 293 else if (prgfunc == 2 && poprnd == 4) 294 pr_cont("SSYNC"); 295 else if (prgfunc == 2 && poprnd == 5) 296 pr_cont("EMUEXCPT"); 297 else if (prgfunc == 3) 298 pr_cont("CLI R%i", poprnd); 299 else if (prgfunc == 4) 300 pr_cont("STI R%i", poprnd); 301 else if (prgfunc == 5) 302 pr_cont("JUMP (P%i)", poprnd); 303 else if (prgfunc == 6) 304 pr_cont("CALL (P%i)", poprnd); 305 else if (prgfunc == 7) 306 pr_cont("CALL (PC + P%i)", poprnd); 307 else if (prgfunc == 8) 308 pr_cont("JUMP (PC + P%i", poprnd); 309 else if (prgfunc == 9) 310 pr_cont("RAISE %i", poprnd); 311 else if (prgfunc == 10) 312 pr_cont("EXCPT %i", poprnd); 313 else 314 pr_cont("0x%04x", opcode); 315 316} 317 318#define BRCC_opcode 0x1000 319#define BRCC_offset_bits 0 320#define BRCC_offset_mask 0x3ff 321#define BRCC_B_bits 10 322#define BRCC_B_mask 0x1 323#define BRCC_T_bits 11 324#define BRCC_T_mask 0x1 325#define BRCC_code_bits 12 326#define BRCC_code_mask 0xf 327 328static void decode_BRCC_0(unsigned int opcode) 329{ 330 int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask); 331 int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask); 332 333 pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : ""); 334} 335 336#define CALLa_opcode 0xe2000000 337#define CALLa_addr_bits 0 338#define CALLa_addr_mask 0xffffff 339#define CALLa_S_bits 24 340#define CALLa_S_mask 0x1 341#define CALLa_code_bits 25 342#define CALLa_code_mask 0x7f 343 344static void decode_CALLa_0(unsigned int opcode) 345{ 346 int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask); 347 348 if (S) 349 pr_cont("CALL pcrel"); 350 else 351 pr_cont("JUMP.L"); 352} 353 354#define LoopSetup_opcode 0xe0800000 355#define LoopSetup_eoffset_bits 0 356#define LoopSetup_eoffset_mask 0x3ff 357#define LoopSetup_dontcare_bits 10 358#define LoopSetup_dontcare_mask 0x3 359#define LoopSetup_reg_bits 12 360#define LoopSetup_reg_mask 0xf 361#define LoopSetup_soffset_bits 16 362#define LoopSetup_soffset_mask 0xf 363#define LoopSetup_c_bits 20 364#define LoopSetup_c_mask 0x1 365#define LoopSetup_rop_bits 21 366#define LoopSetup_rop_mask 0x3 367#define LoopSetup_code_bits 23 368#define LoopSetup_code_mask 0x1ff 369 370static void decode_LoopSetup_0(unsigned int opcode) 371{ 372 int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask); 373 int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask); 374 int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask); 375 376 pr_cont("LSETUP <> LC%i", c); 377 if ((rop & 1) == 1) 378 pr_cont("= P%i", reg); 379 if ((rop & 2) == 2) 380 pr_cont(" >> 0x1"); 381} 382 383#define DspLDST_opcode 0x9c00 384#define DspLDST_reg_bits 0 385#define DspLDST_reg_mask 0x7 386#define DspLDST_i_bits 3 387#define DspLDST_i_mask 0x3 388#define DspLDST_m_bits 5 389#define DspLDST_m_mask 0x3 390#define DspLDST_aop_bits 7 391#define DspLDST_aop_mask 0x3 392#define DspLDST_W_bits 9 393#define DspLDST_W_mask 0x1 394#define DspLDST_code_bits 10 395#define DspLDST_code_mask 0x3f 396 397static void decode_dspLDST_0(unsigned int opcode) 398{ 399 int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask); 400 int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask); 401 int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask); 402 int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask); 403 int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask); 404 405 if (W == 0) { 406 pr_cont("R%i", reg); 407 switch (m) { 408 case 0: 409 pr_cont(" = "); 410 break; 411 case 1: 412 pr_cont(".L = "); 413 break; 414 case 2: 415 pr_cont(".W = "); 416 break; 417 } 418 } 419 420 pr_cont("[ I%i", i); 421 422 switch (aop) { 423 case 0: 424 pr_cont("++ ]"); 425 break; 426 case 1: 427 pr_cont("-- ]"); 428 break; 429 } 430 431 if (W == 1) { 432 pr_cont(" = R%i", reg); 433 switch (m) { 434 case 1: 435 pr_cont(".L = "); 436 break; 437 case 2: 438 pr_cont(".W = "); 439 break; 440 } 441 } 442} 443 444#define LDST_opcode 0x9000 445#define LDST_reg_bits 0 446#define LDST_reg_mask 0x7 447#define LDST_ptr_bits 3 448#define LDST_ptr_mask 0x7 449#define LDST_Z_bits 6 450#define LDST_Z_mask 0x1 451#define LDST_aop_bits 7 452#define LDST_aop_mask 0x3 453#define LDST_W_bits 9 454#define LDST_W_mask 0x1 455#define LDST_sz_bits 10 456#define LDST_sz_mask 0x3 457#define LDST_code_bits 12 458#define LDST_code_mask 0xf 459 460static void decode_LDST_0(unsigned int opcode) 461{ 462 int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask); 463 int W = ((opcode >> LDST_W_bits) & LDST_W_mask); 464 int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask); 465 int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask); 466 int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask); 467 int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask); 468 469 if (W == 0) 470 pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg); 471 472 switch (sz) { 473 case 1: 474 pr_cont("W"); 475 break; 476 case 2: 477 pr_cont("B"); 478 break; 479 } 480 481 pr_cont("[P%i", ptr); 482 483 switch (aop) { 484 case 0: 485 pr_cont("++"); 486 break; 487 case 1: 488 pr_cont("--"); 489 break; 490 } 491 pr_cont("]"); 492 493 if (W == 1) 494 pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg); 495 496 if (sz) { 497 if (Z) 498 pr_cont(" (X)"); 499 else 500 pr_cont(" (Z)"); 501 } 502} 503 504#define LDSTii_opcode 0xa000 505#define LDSTii_reg_bit 0 506#define LDSTii_reg_mask 0x7 507#define LDSTii_ptr_bit 3 508#define LDSTii_ptr_mask 0x7 509#define LDSTii_offset_bit 6 510#define LDSTii_offset_mask 0xf 511#define LDSTii_op_bit 10 512#define LDSTii_op_mask 0x3 513#define LDSTii_W_bit 12 514#define LDSTii_W_mask 0x1 515#define LDSTii_code_bit 13 516#define LDSTii_code_mask 0x7 517 518static void decode_LDSTii_0(unsigned int opcode) 519{ 520 int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask); 521 int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask); 522 int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask); 523 int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask); 524 int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask); 525 526 if (W == 0) { 527 pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg, 528 op == 1 || op == 2 ? "" : "W", ptr, offset); 529 if (op == 2) 530 pr_cont("(Z)"); 531 if (op == 3) 532 pr_cont("(X)"); 533 } else { 534 pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr, 535 offset, op == 3 ? "P" : "R", reg); 536 } 537} 538 539#define LDSTidxI_opcode 0xe4000000 540#define LDSTidxI_offset_bits 0 541#define LDSTidxI_offset_mask 0xffff 542#define LDSTidxI_reg_bits 16 543#define LDSTidxI_reg_mask 0x7 544#define LDSTidxI_ptr_bits 19 545#define LDSTidxI_ptr_mask 0x7 546#define LDSTidxI_sz_bits 22 547#define LDSTidxI_sz_mask 0x3 548#define LDSTidxI_Z_bits 24 549#define LDSTidxI_Z_mask 0x1 550#define LDSTidxI_W_bits 25 551#define LDSTidxI_W_mask 0x1 552#define LDSTidxI_code_bits 26 553#define LDSTidxI_code_mask 0x3f 554 555static void decode_LDSTidxI_0(unsigned int opcode) 556{ 557 int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask); 558 int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask); 559 int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask); 560 int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask); 561 int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask); 562 int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask); 563 564 if (W == 0) 565 pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg); 566 567 if (sz == 1) 568 pr_cont("W"); 569 if (sz == 2) 570 pr_cont("B"); 571 572 pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "", 573 (offset & 0x1f) << 2); 574 575 if (W == 0 && sz != 0) { 576 if (Z) 577 pr_cont("(X)"); 578 else 579 pr_cont("(Z)"); 580 } 581 582 if (W == 1) 583 pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg); 584 585} 586 587static void decode_opcode(unsigned int opcode) 588{ 589#ifdef CONFIG_BUG 590 if (opcode == BFIN_BUG_OPCODE) 591 pr_cont("BUG"); 592 else 593#endif 594 if ((opcode & 0xffffff00) == ProgCtrl_opcode) 595 decode_ProgCtrl_0(opcode); 596 else if ((opcode & 0xfffff000) == BRCC_opcode) 597 decode_BRCC_0(opcode); 598 else if ((opcode & 0xfffff000) == 0x2000) 599 pr_cont("JUMP.S"); 600 else if ((opcode & 0xfe000000) == CALLa_opcode) 601 decode_CALLa_0(opcode); 602 else if ((opcode & 0xff8000C0) == LoopSetup_opcode) 603 decode_LoopSetup_0(opcode); 604 else if ((opcode & 0xfffffc00) == DspLDST_opcode) 605 decode_dspLDST_0(opcode); 606 else if ((opcode & 0xfffff000) == LDST_opcode) 607 decode_LDST_0(opcode); 608 else if ((opcode & 0xffffe000) == LDSTii_opcode) 609 decode_LDSTii_0(opcode); 610 else if ((opcode & 0xfc000000) == LDSTidxI_opcode) 611 decode_LDSTidxI_0(opcode); 612 else if (opcode & 0xffff0000) 613 pr_cont("0x%08x", opcode); 614 else 615 pr_cont("0x%04x", opcode); 616} 617 618#define BIT_MULTI_INS 0x08000000 619static void decode_instruction(unsigned short *address) 620{ 621 unsigned int opcode; 622 623 if (!get_instruction(&opcode, address)) 624 return; 625 626 decode_opcode(opcode); 627 628 /* If things are a 32-bit instruction, it has the possibility of being 629 * a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions) 630 * This test collidates with the unlink instruction, so disallow that 631 */ 632 if ((opcode & 0xc0000000) == 0xc0000000 && 633 (opcode & BIT_MULTI_INS) && 634 (opcode & 0xe8000000) != 0xe8000000) { 635 pr_cont(" || "); 636 if (!get_instruction(&opcode, address + 2)) 637 return; 638 decode_opcode(opcode); 639 pr_cont(" || "); 640 if (!get_instruction(&opcode, address + 3)) 641 return; 642 decode_opcode(opcode); 643 } 644} 645#endif 646 647void dump_bfin_trace_buffer(void) 648{ 649#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON 650 int tflags, i = 0, fault = 0; 651 char buf[150]; 652 unsigned short *addr; 653 unsigned int cpu = raw_smp_processor_id(); 654#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND 655 int j, index; 656#endif 657 658 trace_buffer_save(tflags); 659 660 pr_notice("Hardware Trace:\n"); 661 662#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND 663 pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n"); 664#endif 665 666 if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) { 667 for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) { 668 addr = (unsigned short *)bfin_read_TBUF(); 669 decode_address(buf, (unsigned long)addr); 670 pr_notice("%4i Target : %s\n", i, buf); 671 /* Normally, the faulting instruction doesn't go into 672 * the trace buffer, (since it doesn't commit), so 673 * we print out the fault address here 674 */ 675 if (!fault && addr == ((unsigned short *)evt_ivhw)) { 676 addr = (unsigned short *)bfin_read_TBUF(); 677 decode_address(buf, (unsigned long)addr); 678 pr_notice(" FAULT : %s ", buf); 679 decode_instruction(addr); 680 pr_cont("\n"); 681 fault = 1; 682 continue; 683 } 684 if (!fault && addr == (unsigned short *)trap && 685 (cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE) > VEC_EXCPT15) { 686 decode_address(buf, cpu_pda[cpu].icplb_fault_addr); 687 pr_notice(" FAULT : %s ", buf); 688 decode_instruction((unsigned short *)cpu_pda[cpu].icplb_fault_addr); 689 pr_cont("\n"); 690 fault = 1; 691 } 692 addr = (unsigned short *)bfin_read_TBUF(); 693 decode_address(buf, (unsigned long)addr); 694 pr_notice(" Source : %s ", buf); 695 decode_instruction(addr); 696 pr_cont("\n"); 697 } 698 } 699 700#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND 701 if (trace_buff_offset) 702 index = trace_buff_offset / 4; 703 else 704 index = EXPAND_LEN; 705 706 j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128; 707 while (j) { 708 decode_address(buf, software_trace_buff[index]); 709 pr_notice("%4i Target : %s\n", i, buf); 710 index -= 1; 711 if (index < 0) 712 index = EXPAND_LEN; 713 decode_address(buf, software_trace_buff[index]); 714 pr_notice(" Source : %s ", buf); 715 decode_instruction((unsigned short *)software_trace_buff[index]); 716 pr_cont("\n"); 717 index -= 1; 718 if (index < 0) 719 index = EXPAND_LEN; 720 j--; 721 i++; 722 } 723#endif 724 725 trace_buffer_restore(tflags); 726#endif 727} 728EXPORT_SYMBOL(dump_bfin_trace_buffer); 729 730void dump_bfin_process(struct pt_regs *fp) 731{ 732 /* We should be able to look at fp->ipend, but we don't push it on the 733 * stack all the time, so do this until we fix that */ 734 unsigned int context = bfin_read_IPEND(); 735 736 if (oops_in_progress) 737 pr_emerg("Kernel OOPS in progress\n"); 738 739 if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) 740 pr_notice("HW Error context\n"); 741 else if (context & 0x0020) 742 pr_notice("Deferred Exception context\n"); 743 else if (context & 0x3FC0) 744 pr_notice("Interrupt context\n"); 745 else if (context & 0x4000) 746 pr_notice("Deferred Interrupt context\n"); 747 else if (context & 0x8000) 748 pr_notice("Kernel process context\n"); 749 750 /* Because we are crashing, and pointers could be bad, we check things 751 * pretty closely before we use them 752 */ 753 if ((unsigned long)current >= FIXED_CODE_START && 754 !((unsigned long)current & 0x3) && current->pid) { 755 pr_notice("CURRENT PROCESS:\n"); 756 if (current->comm >= (char *)FIXED_CODE_START) 757 pr_notice("COMM=%s PID=%d", 758 current->comm, current->pid); 759 else 760 pr_notice("COMM= invalid"); 761 762 pr_cont(" CPU=%d\n", current_thread_info()->cpu); 763 if (!((unsigned long)current->mm & 0x3) && 764 (unsigned long)current->mm >= FIXED_CODE_START) { 765 pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n", 766 (void *)current->mm->start_code, 767 (void *)current->mm->end_code, 768 (void *)current->mm->start_data, 769 (void *)current->mm->end_data); 770 pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n", 771 (void *)current->mm->end_data, 772 (void *)current->mm->brk, 773 (void *)current->mm->start_stack); 774 } else 775 pr_notice("invalid mm\n"); 776 } else 777 pr_notice("No Valid process in current context\n"); 778} 779 780void dump_bfin_mem(struct pt_regs *fp) 781{ 782 unsigned short *addr, *erraddr, val = 0, err = 0; 783 char sti = 0, buf[6]; 784 785 erraddr = (void *)fp->pc; 786 787 pr_notice("return address: [0x%p]; contents of:", erraddr); 788 789 for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10; 790 addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10; 791 addr++) { 792 if (!((unsigned long)addr & 0xF)) 793 pr_notice("0x%p: ", addr); 794 795 if (!get_mem16(&val, addr)) { 796 val = 0; 797 sprintf(buf, "????"); 798 } else 799 sprintf(buf, "%04x", val); 800 801 if (addr == erraddr) { 802 pr_cont("[%s]", buf); 803 err = val; 804 } else 805 pr_cont(" %s ", buf); 806 807 /* Do any previous instructions turn on interrupts? */ 808 if (addr <= erraddr && /* in the past */ 809 ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */ 810 val == 0x017b)) /* [SP++] = RETI */ 811 sti = 1; 812 } 813 814 pr_cont("\n"); 815 816 /* Hardware error interrupts can be deferred */ 817 if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR && 818 oops_in_progress)){ 819 pr_notice("Looks like this was a deferred error - sorry\n"); 820#ifndef CONFIG_DEBUG_HWERR 821 pr_notice("The remaining message may be meaningless\n"); 822 pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n"); 823#else 824 /* If we are handling only one peripheral interrupt 825 * and current mm and pid are valid, and the last error 826 * was in that user space process's text area 827 * print it out - because that is where the problem exists 828 */ 829 if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) && 830 (current->pid && current->mm)) { 831 /* And the last RETI points to the current userspace context */ 832 if ((fp + 1)->pc >= current->mm->start_code && 833 (fp + 1)->pc <= current->mm->end_code) { 834 pr_notice("It might be better to look around here :\n"); 835 pr_notice("-------------------------------------------\n"); 836 show_regs(fp + 1); 837 pr_notice("-------------------------------------------\n"); 838 } 839 } 840#endif 841 } 842} 843 844void show_regs(struct pt_regs *fp) 845{ 846 char buf[150]; 847 struct irqaction *action; 848 unsigned int i; 849 unsigned long flags = 0; 850 unsigned int cpu = raw_smp_processor_id(); 851 unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); 852 853 pr_notice("\n"); 854 if (CPUID != bfin_cpuid()) 855 pr_notice("Compiled for cpu family 0x%04x (Rev %d), " 856 "but running on:0x%04x (Rev %d)\n", 857 CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid()); 858 859 pr_notice("ADSP-%s-0.%d", 860 CPU, bfin_compiled_revid()); 861 862 if (bfin_compiled_revid() != bfin_revid()) 863 pr_cont("(Detected 0.%d)", bfin_revid()); 864 865 pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n", 866 get_cclk()/1000000, get_sclk()/1000000, 867#ifdef CONFIG_MPU 868 "mpu on" 869#else 870 "mpu off" 871#endif 872 ); 873 874 pr_notice("%s", linux_banner); 875 876 pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted()); 877 pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n", 878 (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg); 879 if (fp->ipend & EVT_IRPTEN) 880 pr_notice(" Global Interrupts Disabled (IPEND[4])\n"); 881 if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 | 882 EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR))) 883 pr_notice(" Peripheral interrupts masked off\n"); 884 if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14))) 885 pr_notice(" Kernel interrupts masked off\n"); 886 if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) { 887 pr_notice(" HWERRCAUSE: 0x%lx\n", 888 (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14); 889#ifdef EBIU_ERRMST 890 /* If the error was from the EBIU, print it out */ 891 if (bfin_read_EBIU_ERRMST() & CORE_ERROR) { 892 pr_notice(" EBIU Error Reason : 0x%04x\n", 893 bfin_read_EBIU_ERRMST()); 894 pr_notice(" EBIU Error Address : 0x%08x\n", 895 bfin_read_EBIU_ERRADD()); 896 } 897#endif 898 } 899 pr_notice(" EXCAUSE : 0x%lx\n", 900 fp->seqstat & SEQSTAT_EXCAUSE); 901 for (i = 2; i <= 15 ; i++) { 902 if (fp->ipend & (1 << i)) { 903 if (i != 4) { 904 decode_address(buf, bfin_read32(EVT0 + 4*i)); 905 pr_notice(" physical IVG%i asserted : %s\n", i, buf); 906 } else 907 pr_notice(" interrupts disabled\n"); 908 } 909 } 910 911 /* if no interrupts are going off, don't print this out */ 912 if (fp->ipend & ~0x3F) { 913 for (i = 0; i < (NR_IRQS - 1); i++) { 914 if (!in_atomic) 915 raw_spin_lock_irqsave(&irq_desc[i].lock, flags); 916 917 action = irq_desc[i].action; 918 if (!action) 919 goto unlock; 920 921 decode_address(buf, (unsigned int)action->handler); 922 pr_notice(" logical irq %3d mapped : %s", i, buf); 923 for (action = action->next; action; action = action->next) { 924 decode_address(buf, (unsigned int)action->handler); 925 pr_cont(", %s", buf); 926 } 927 pr_cont("\n"); 928unlock: 929 if (!in_atomic) 930 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); 931 } 932 } 933 934 decode_address(buf, fp->rete); 935 pr_notice(" RETE: %s\n", buf); 936 decode_address(buf, fp->retn); 937 pr_notice(" RETN: %s\n", buf); 938 decode_address(buf, fp->retx); 939 pr_notice(" RETX: %s\n", buf); 940 decode_address(buf, fp->rets); 941 pr_notice(" RETS: %s\n", buf); 942 decode_address(buf, fp->pc); 943 pr_notice(" PC : %s\n", buf); 944 945 if (((long)fp->seqstat & SEQSTAT_EXCAUSE) && 946 (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) { 947 decode_address(buf, cpu_pda[cpu].dcplb_fault_addr); 948 pr_notice("DCPLB_FAULT_ADDR: %s\n", buf); 949 decode_address(buf, cpu_pda[cpu].icplb_fault_addr); 950 pr_notice("ICPLB_FAULT_ADDR: %s\n", buf); 951 } 952 953 pr_notice("PROCESSOR STATE:\n"); 954 pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", 955 fp->r0, fp->r1, fp->r2, fp->r3); 956 pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n", 957 fp->r4, fp->r5, fp->r6, fp->r7); 958 pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n", 959 fp->p0, fp->p1, fp->p2, fp->p3); 960 pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n", 961 fp->p4, fp->p5, fp->fp, (long)fp); 962 pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n", 963 fp->lb0, fp->lt0, fp->lc0); 964 pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n", 965 fp->lb1, fp->lt1, fp->lc1); 966 pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n", 967 fp->b0, fp->l0, fp->m0, fp->i0); 968 pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n", 969 fp->b1, fp->l1, fp->m1, fp->i1); 970 pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n", 971 fp->b2, fp->l2, fp->m2, fp->i2); 972 pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n", 973 fp->b3, fp->l3, fp->m3, fp->i3); 974 pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", 975 fp->a0w, fp->a0x, fp->a1w, fp->a1x); 976 977 pr_notice("USP : %08lx ASTAT: %08lx\n", 978 rdusp(), fp->astat); 979 980 pr_notice("\n"); 981} 982