1/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h 2 * 3 * Copyright 2008 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * http://armlinux.simtec.co.uk/ 6 * 7 * S3C24xx - common pll registers and code 8 */ 9 10#define S3C24XX_PLLCON_MDIVSHIFT 12 11#define S3C24XX_PLLCON_PDIVSHIFT 4 12#define S3C24XX_PLLCON_SDIVSHIFT 0 13#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) 14#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1) 15#define S3C24XX_PLLCON_SDIVMASK 3 16 17#include <asm/div64.h> 18 19static inline unsigned int 20s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk) 21{ 22 unsigned int mdiv, pdiv, sdiv; 23 uint64_t fvco; 24 25 mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT; 26 pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT; 27 sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT; 28 29 mdiv &= S3C24XX_PLLCON_MDIVMASK; 30 pdiv &= S3C24XX_PLLCON_PDIVMASK; 31 sdiv &= S3C24XX_PLLCON_SDIVMASK; 32 33 fvco = (uint64_t)baseclk * (mdiv + 8); 34 do_div(fvco, (pdiv + 2) << sdiv); 35 36 return (unsigned int)fvco; 37} 38 39#define S3C2416_PLL_M_SHIFT (14) 40#define S3C2416_PLL_P_SHIFT (5) 41#define S3C2416_PLL_S_MASK (7) 42#define S3C2416_PLL_M_MASK ((1 << 10) - 1) 43#define S3C2416_PLL_P_MASK (63) 44 45static inline unsigned int 46s3c2416_get_pll(unsigned int pllval, unsigned int baseclk) 47{ 48 unsigned int m, p, s; 49 uint64_t fvco; 50 51 m = pllval >> S3C2416_PLL_M_SHIFT; 52 p = pllval >> S3C2416_PLL_P_SHIFT; 53 54 s = pllval & S3C2416_PLL_S_MASK; 55 m &= S3C2416_PLL_M_MASK; 56 p &= S3C2416_PLL_P_MASK; 57 58 fvco = (uint64_t)baseclk * m; 59 do_div(fvco, (p << s)); 60 61 return (unsigned int)fvco; 62} 63