1/* 2 * arch/arm/plat-orion/time.c 3 * 4 * Marvell Orion SoC timer handling. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 * 10 * Timer 0 is used as free-running clocksource, while timer 1 is 11 * used as clock_event_device. 12 */ 13 14#include <linux/kernel.h> 15#include <linux/sched.h> 16#include <linux/cnt32_to_63.h> 17#include <linux/timer.h> 18#include <linux/clockchips.h> 19#include <linux/interrupt.h> 20#include <linux/irq.h> 21#include <asm/mach/time.h> 22#include <mach/bridge-regs.h> 23#include <mach/hardware.h> 24 25/* 26 * Number of timer ticks per jiffy. 27 */ 28static u32 ticks_per_jiffy; 29 30 31/* 32 * Timer block registers. 33 */ 34#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) 35#define TIMER0_EN 0x0001 36#define TIMER0_RELOAD_EN 0x0002 37#define TIMER1_EN 0x0004 38#define TIMER1_RELOAD_EN 0x0008 39#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010) 40#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014) 41#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018) 42#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c) 43 44 45/* 46 * Orion's sched_clock implementation. It has a resolution of 47 * at least 7.5ns (133MHz TCLK) and a maximum value of 834 days. 48 * 49 * Because the hardware timer period is quite short (21 secs if 50 * 200MHz TCLK) and because cnt32_to_63() needs to be called at 51 * least once per half period to work properly, a kernel timer is 52 * set up to ensure this requirement is always met. 53 */ 54#define TCLK2NS_SCALE_FACTOR 8 55 56static unsigned long tclk2ns_scale; 57 58unsigned long long sched_clock(void) 59{ 60 unsigned long long v = cnt32_to_63(0xffffffff - readl(TIMER0_VAL)); 61 return (v * tclk2ns_scale) >> TCLK2NS_SCALE_FACTOR; 62} 63 64static struct timer_list cnt32_to_63_keepwarm_timer; 65 66static void cnt32_to_63_keepwarm(unsigned long data) 67{ 68 mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); 69 (void) sched_clock(); 70} 71 72static void __init setup_sched_clock(unsigned long tclk) 73{ 74 unsigned long long v; 75 unsigned long data; 76 77 v = NSEC_PER_SEC; 78 v <<= TCLK2NS_SCALE_FACTOR; 79 v += tclk/2; 80 do_div(v, tclk); 81 /* 82 * We want an even value to automatically clear the top bit 83 * returned by cnt32_to_63() without an additional run time 84 * instruction. So if the LSB is 1 then round it up. 85 */ 86 if (v & 1) 87 v++; 88 tclk2ns_scale = v; 89 90 data = (0xffffffffUL / tclk / 2 - 2) * HZ; 91 setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data); 92 mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); 93} 94 95/* 96 * Clocksource handling. 97 */ 98static cycle_t orion_clksrc_read(struct clocksource *cs) 99{ 100 return 0xffffffff - readl(TIMER0_VAL); 101} 102 103static struct clocksource orion_clksrc = { 104 .name = "orion_clocksource", 105 .shift = 20, 106 .rating = 300, 107 .read = orion_clksrc_read, 108 .mask = CLOCKSOURCE_MASK(32), 109 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 110}; 111 112 113 114/* 115 * Clockevent handling. 116 */ 117static int 118orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) 119{ 120 unsigned long flags; 121 u32 u; 122 123 if (delta == 0) 124 return -ETIME; 125 126 local_irq_save(flags); 127 128 /* 129 * Clear and enable clockevent timer interrupt. 130 */ 131 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); 132 133 u = readl(BRIDGE_MASK); 134 u |= BRIDGE_INT_TIMER1; 135 writel(u, BRIDGE_MASK); 136 137 /* 138 * Setup new clockevent timer value. 139 */ 140 writel(delta, TIMER1_VAL); 141 142 /* 143 * Enable the timer. 144 */ 145 u = readl(TIMER_CTRL); 146 u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN; 147 writel(u, TIMER_CTRL); 148 149 local_irq_restore(flags); 150 151 return 0; 152} 153 154static void 155orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) 156{ 157 unsigned long flags; 158 u32 u; 159 160 local_irq_save(flags); 161 if (mode == CLOCK_EVT_MODE_PERIODIC) { 162 /* 163 * Setup timer to fire at 1/HZ intervals. 164 */ 165 writel(ticks_per_jiffy - 1, TIMER1_RELOAD); 166 writel(ticks_per_jiffy - 1, TIMER1_VAL); 167 168 /* 169 * Enable timer interrupt. 170 */ 171 u = readl(BRIDGE_MASK); 172 writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK); 173 174 /* 175 * Enable timer. 176 */ 177 u = readl(TIMER_CTRL); 178 writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL); 179 } else { 180 /* 181 * Disable timer. 182 */ 183 u = readl(TIMER_CTRL); 184 writel(u & ~TIMER1_EN, TIMER_CTRL); 185 186 /* 187 * Disable timer interrupt. 188 */ 189 u = readl(BRIDGE_MASK); 190 writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK); 191 192 /* 193 * ACK pending timer interrupt. 194 */ 195 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); 196 197 } 198 local_irq_restore(flags); 199} 200 201static struct clock_event_device orion_clkevt = { 202 .name = "orion_tick", 203 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, 204 .shift = 32, 205 .rating = 300, 206 .set_next_event = orion_clkevt_next_event, 207 .set_mode = orion_clkevt_mode, 208}; 209 210static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) 211{ 212 /* 213 * ACK timer interrupt and call event handler. 214 */ 215 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); 216 orion_clkevt.event_handler(&orion_clkevt); 217 218 return IRQ_HANDLED; 219} 220 221static struct irqaction orion_timer_irq = { 222 .name = "orion_tick", 223 .flags = IRQF_DISABLED | IRQF_TIMER, 224 .handler = orion_timer_interrupt 225}; 226 227void __init orion_time_init(unsigned int irq, unsigned int tclk) 228{ 229 u32 u; 230 231 ticks_per_jiffy = (tclk + HZ/2) / HZ; 232 233 /* 234 * Set scale and timer for sched_clock 235 */ 236 setup_sched_clock(tclk); 237 238 /* 239 * Setup free-running clocksource timer (interrupts 240 * disabled.) 241 */ 242 writel(0xffffffff, TIMER0_VAL); 243 writel(0xffffffff, TIMER0_RELOAD); 244 u = readl(BRIDGE_MASK); 245 writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); 246 u = readl(TIMER_CTRL); 247 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); 248 orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift); 249 clocksource_register(&orion_clksrc); 250 251 /* 252 * Setup clockevent timer (interrupt-driven.) 253 */ 254 setup_irq(irq, &orion_timer_irq); 255 orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); 256 orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); 257 orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); 258 orion_clkevt.cpumask = cpumask_of(0); 259 clockevents_register_device(&orion_clkevt); 260} 261