1/* 2 * arch/arm/plat-omap/include/mach/control.h 3 * 4 * OMAP2/3/4 System Control Module definitions 5 * 6 * Copyright (C) 2007-2009 Texas Instruments, Inc. 7 * Copyright (C) 2007-2008 Nokia Corporation 8 * 9 * Written by Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation. 14 */ 15 16#ifndef __ASM_ARCH_CONTROL_H 17#define __ASM_ARCH_CONTROL_H 18 19#include <mach/io.h> 20 21#ifndef __ASSEMBLY__ 22#define OMAP242X_CTRL_REGADDR(reg) \ 23 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 24#define OMAP243X_CTRL_REGADDR(reg) \ 25 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 26#define OMAP343X_CTRL_REGADDR(reg) \ 27 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 28#else 29#define OMAP242X_CTRL_REGADDR(reg) \ 30 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 31#define OMAP243X_CTRL_REGADDR(reg) \ 32 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 33#define OMAP343X_CTRL_REGADDR(reg) \ 34 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 35#endif /* __ASSEMBLY__ */ 36 37/* 38 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for 39 * OMAP24XX and OMAP34XX. 40 */ 41 42/* Control submodule offsets */ 43 44#define OMAP2_CONTROL_INTERFACE 0x000 45#define OMAP2_CONTROL_PADCONFS 0x030 46#define OMAP2_CONTROL_GENERAL 0x270 47#define OMAP343X_CONTROL_MEM_WKUP 0x600 48#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 49#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 50 51/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ 52 53#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) 54 55/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ 56#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) 57#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) 58#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) 59#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) 60#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) 61#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) 62#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) 63#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) 64#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) 65#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) 66#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) 67#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) 68 69/* 242x-only CONTROL_GENERAL register offsets */ 70#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ 71#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) 72 73/* 243x-only CONTROL_GENERAL register offsets */ 74/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ 75#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) 76#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) 77#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 78#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 79#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) 80#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) 81 82/* 24xx-only CONTROL_GENERAL register offsets */ 83#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) 84#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) 85#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) 86#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) 87#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) 88#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) 89#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) 90#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) 91#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) 92#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) 93#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) 94#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 95#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 96#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) 97#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) 98#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) 99#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) 100#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) 101#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) 102#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) 103#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) 104#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) 105#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) 106#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) 107#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) 108#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) 109#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) 110#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) 111#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) 112#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) 113#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) 114 115#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) 116 117/* 34xx-only CONTROL_GENERAL register offsets */ 118#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) 119#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) 120#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) 121#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) 122#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) 123#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) 124#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) 125#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) 126#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 127#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 128#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) 129#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) 130#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) 131#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) 132#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) 133#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) 134#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) 135#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) 136#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) 137#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) 138#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) 139#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) 140#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) 141#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) 142#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) 143#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) 144#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) 145#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) 146#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 147#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 148#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 149#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ 150 + ((i) >> 1) * 4 + (!((i) & 1)) * 2) 151#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) 152#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) 153#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) 154#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) 155#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) 156#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) 157#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) 158#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) 159#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) 160#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) 161#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) 162 163/* AM35XX only CONTROL_GENERAL register offsets */ 164#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) 165#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) 166#define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) 167#define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) 168#define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) 169#define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) 170#define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) 171 172/* 34xx PADCONF register offsets */ 173#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ 174 (i)*2) 175#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) 176#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) 177#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) 178#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) 179#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) 180#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) 181#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) 182#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) 183#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) 184#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) 185#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) 186#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) 187#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) 188#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) 189#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) 190#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) 191#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) 192#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) 193 194/* 34xx GENERAL_WKUP regist offsets */ 195#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ 196 0x008 + (i)) 197#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) 198#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) 199#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) 200#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) 201#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) 202 203/* 34xx D2D idle-related pins, handled by PM core */ 204#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 205#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 206 207/* 44xx control status register offset */ 208#define OMAP44XX_CONTROL_STATUS 0x2c4 209 210/* 44xx-only CONTROL_GENERAL register offsets */ 211#define OMAP44XX_CONTROL_MMC1 0x628 212#define OMAP44XX_CONTROL_PBIAS_LITE 0x600 213/* 214 * REVISIT: This list of registers is not comprehensive - there are more 215 * that should be added. 216 */ 217 218/* 219 * Control module register bit defines - these should eventually go into 220 * their own regbits file. Some of these will be complicated, depending 221 * on the device type (general-purpose, emulator, test, secure, bad, other) 222 * and the security mode (secure, non-secure, don't care) 223 */ 224/* CONTROL_DEVCONF0 bits */ 225#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ 226#define OMAP24XX_USBSTANDBYCTRL (1 << 15) 227#define OMAP2_MCBSP2_CLKS_MASK (1 << 6) 228#define OMAP2_MCBSP1_CLKS_MASK (1 << 2) 229 230/* CONTROL_DEVCONF1 bits */ 231#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) 232#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ 233#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ 234#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ 235#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ 236 237/* CONTROL_STATUS bits */ 238#define OMAP2_DEVICETYPE_MASK (0x7 << 8) 239#define OMAP2_SYSBOOT_5_MASK (1 << 5) 240#define OMAP2_SYSBOOT_4_MASK (1 << 4) 241#define OMAP2_SYSBOOT_3_MASK (1 << 3) 242#define OMAP2_SYSBOOT_2_MASK (1 << 2) 243#define OMAP2_SYSBOOT_1_MASK (1 << 1) 244#define OMAP2_SYSBOOT_0_MASK (1 << 0) 245 246/* CONTROL_PBIAS_LITE bits */ 247#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) 248#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) 249#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) 250#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) 251#define OMAP343X_PBIASLITEVMODE1 (1 << 8) 252#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) 253#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) 254#define OMAP2_PBIASSPEEDCTRL0 (1 << 2) 255#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 256#define OMAP2_PBIASLITEVMODE0 (1 << 0) 257 258/* CONTROL_PBIAS_LITE bits for OMAP4 */ 259#define OMAP4_MMC1_PWRDNZ (1 << 26) 260#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25) 261#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24) 262#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23) 263#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22) 264#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21) 265#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20) 266 267#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31) 268#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30) 269#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29) 270#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28) 271#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27) 272#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26) 273#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25) 274 275/* CONTROL_PROG_IO1 bits */ 276#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) 277 278/* CONTROL_IVA2_BOOTMOD bits */ 279#define OMAP3_IVA2_BOOTMOD_SHIFT 0 280#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) 281#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) 282 283/* CONTROL_PADCONF_X bits */ 284#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) 285#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) 286 287#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) 288#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) 289#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C 290 291/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ 292#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 293#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 294#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 295#define AM35XX_HECC_VBUSP_CLK_SHIFT 3 296#define AM35XX_USBOTG_FCLK_SHIFT 8 297#define AM35XX_CPGMAC_FCLK_SHIFT 9 298#define AM35XX_VPFE_FCLK_SHIFT 10 299 300/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ 301#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) 302#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) 303#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) 304#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) 305#define AM35XX_USBOTGSS_INT_CLR BIT(4) 306#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) 307#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) 308#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) 309 310/*AM35XX CONTROL_IP_SW_RESET bits*/ 311#define AM35XX_USBOTGSS_SW_RST BIT(0) 312#define AM35XX_CPGMACSS_SW_RST BIT(1) 313#define AM35XX_VPFE_VBUSP_SW_RST BIT(2) 314#define AM35XX_HECC_SW_RST BIT(3) 315#define AM35XX_VPFE_PCLK_SW_RST BIT(4) 316 317/* 318 * CONTROL OMAP STATUS register to identify OMAP3 features 319 */ 320#define OMAP3_CONTROL_OMAP_STATUS 0x044c 321 322#define OMAP3_SGX_SHIFT 13 323#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT) 324#define FEAT_SGX_FULL 0 325#define FEAT_SGX_HALF 1 326#define FEAT_SGX_NONE 2 327 328#define OMAP3_IVA_SHIFT 12 329#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT) 330#define FEAT_IVA 0 331#define FEAT_IVA_NONE 1 332 333#define OMAP3_L2CACHE_SHIFT 10 334#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT) 335#define FEAT_L2CACHE_NONE 0 336#define FEAT_L2CACHE_64KB 1 337#define FEAT_L2CACHE_128KB 2 338#define FEAT_L2CACHE_256KB 3 339 340#define OMAP3_ISP_SHIFT 5 341#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT) 342#define FEAT_ISP 0 343#define FEAT_ISP_NONE 1 344 345#define OMAP3_NEON_SHIFT 4 346#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT) 347#define FEAT_NEON 0 348#define FEAT_NEON_NONE 1 349 350 351#ifndef __ASSEMBLY__ 352#ifdef CONFIG_ARCH_OMAP2PLUS 353extern void __iomem *omap_ctrl_base_get(void); 354extern u8 omap_ctrl_readb(u16 offset); 355extern u16 omap_ctrl_readw(u16 offset); 356extern u32 omap_ctrl_readl(u16 offset); 357extern void omap_ctrl_writeb(u8 val, u16 offset); 358extern void omap_ctrl_writew(u16 val, u16 offset); 359extern void omap_ctrl_writel(u32 val, u16 offset); 360 361extern void omap3_save_scratchpad_contents(void); 362extern void omap3_clear_scratchpad_contents(void); 363extern u32 *get_restore_pointer(void); 364extern u32 *get_es3_restore_pointer(void); 365extern u32 omap3_arm_context[128]; 366extern void omap3_control_save_context(void); 367extern void omap3_control_restore_context(void); 368 369#else 370#define omap_ctrl_base_get() 0 371#define omap_ctrl_readb(x) 0 372#define omap_ctrl_readw(x) 0 373#define omap_ctrl_readl(x) 0 374#define omap_ctrl_writeb(x, y) WARN_ON(1) 375#define omap_ctrl_writew(x, y) WARN_ON(1) 376#define omap_ctrl_writel(x, y) WARN_ON(1) 377#endif 378#endif /* __ASSEMBLY__ */ 379 380#endif /* __ASM_ARCH_CONTROL_H */ 381