1/* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 */ 4 5/* 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#ifndef __MACH_MX3x_H__ 12#define __MACH_MX3x_H__ 13 14/* 15 * MX31 memory map: 16 * 17 * Virt Phys Size What 18 * --------------------------------------------------------------------------- 19 * FC000000 43F00000 1M AIPS 1 20 * FC100000 50000000 1M SPBA 21 * FC200000 53F00000 1M AIPS 2 22 * FC500000 60000000 128M ROMPATCH 23 * FC400000 68000000 128M AVIC 24 * 70000000 256M IPU (MAX M2) 25 * 80000000 256M CSD0 SDRAM/DDR 26 * 90000000 256M CSD1 SDRAM/DDR 27 * A0000000 128M CS0 Flash 28 * A8000000 128M CS1 Flash 29 * B0000000 32M CS2 30 * B2000000 32M CS3 31 * F4000000 B4000000 32M CS4 32 * B6000000 32M CS5 33 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers 34 * C0000000 64M PCMCIA/CF 35 */ 36 37/* 38 * L2CC 39 */ 40#define MX3x_L2CC_BASE_ADDR 0x30000000 41#define MX3x_L2CC_SIZE SZ_1M 42 43/* 44 * AIPS 1 45 */ 46#define MX3x_AIPS1_BASE_ADDR 0x43f00000 47#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000 48#define MX3x_AIPS1_SIZE SZ_1M 49#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) 50#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) 51#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000) 52#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000) 53#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000) 54#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000) 55#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000) 56#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000) 57#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000) 58#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000) 59#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000) 60#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000) 61#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000) 62#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000) 63#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000) 64#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000) 65#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000) 66#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000) 67 68/* 69 * SPBA global module enabled #0 70 */ 71#define MX3x_SPBA0_BASE_ADDR 0x50000000 72#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000 73#define MX3x_SPBA0_SIZE SZ_1M 74#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) 75#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) 76#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000) 77#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000) 78#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000) 79#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000) 80 81/* 82 * AIPS 2 83 */ 84#define MX3x_AIPS2_BASE_ADDR 0x53f00000 85#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000 86#define MX3x_AIPS2_SIZE SZ_1M 87#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) 88#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) 89#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000) 90#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000) 91#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000) 92#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000) 93#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000) 94#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000) 95#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000) 96#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000) 97#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000) 98#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000) 99#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000) 100#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000) 101#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000) 102#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000) 103 104/* 105 * ROMP and AVIC 106 */ 107#define MX3x_ROMP_BASE_ADDR 0x60000000 108#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000 109#define MX3x_ROMP_SIZE SZ_1M 110 111#define MX3x_AVIC_BASE_ADDR 0x68000000 112#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000 113#define MX3x_AVIC_SIZE SZ_1M 114 115/* 116 * Memory regions and CS 117 */ 118#define MX3x_IPU_MEM_BASE_ADDR 0x70000000 119#define MX3x_CSD0_BASE_ADDR 0x80000000 120#define MX3x_CSD1_BASE_ADDR 0x90000000 121 122#define MX3x_CS0_BASE_ADDR 0xa0000000 123#define MX3x_CS1_BASE_ADDR 0xa8000000 124#define MX3x_CS2_BASE_ADDR 0xb0000000 125#define MX3x_CS3_BASE_ADDR 0xb2000000 126 127#define MX3x_CS4_BASE_ADDR 0xb4000000 128#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000 129#define MX3x_CS4_SIZE SZ_32M 130 131#define MX3x_CS5_BASE_ADDR 0xb6000000 132#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000 133#define MX3x_CS5_SIZE SZ_32M 134 135/* 136 * NAND, SDRAM, WEIM, M3IF, EMI controllers 137 */ 138#define MX3x_X_MEMC_BASE_ADDR 0xb8000000 139#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000 140#define MX3x_X_MEMC_SIZE SZ_64K 141#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) 142#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) 143#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000) 144#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000) 145#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR 146 147#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 148 149/*! 150 * This macro defines the physical to virtual address mapping for all the 151 * peripheral modules. It is used by passing in the physical address as x 152 * and returning the virtual address. If the physical address is not mapped, 153 * it returns 0xDEADBEEF 154 */ 155#define IO_ADDRESS(x) \ 156 (void __force __iomem *) \ 157 (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ 158 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ 159 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ 160 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ 161 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ 162 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ 163 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ 164 0xDEADBEEF) 165 166/* 167 * define the address mapping macros: in physical address order 168 */ 169#define L2CC_IO_ADDRESS(x) \ 170 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) 171 172#define AIPS1_IO_ADDRESS(x) \ 173 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) 174 175#define SPBA0_IO_ADDRESS(x) \ 176 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) 177 178#define AIPS2_IO_ADDRESS(x) \ 179 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) 180 181#define ROMP_IO_ADDRESS(x) \ 182 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) 183 184#define AVIC_IO_ADDRESS(x) \ 185 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) 186 187#define CS4_IO_ADDRESS(x) \ 188 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) 189 190#define CS5_IO_ADDRESS(x) \ 191 (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT) 192 193#define X_MEMC_IO_ADDRESS(x) \ 194 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) 195 196#define PCMCIA_IO_ADDRESS(x) \ 197 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) 198 199/* 200 * Interrupt numbers 201 */ 202#define MX3x_INT_I2C3 3 203#define MX3x_INT_I2C2 4 204#define MX3x_INT_RTIC 6 205#define MX3x_INT_I2C 10 206#define MX3x_INT_CSPI2 13 207#define MX3x_INT_CSPI1 14 208#define MX3x_INT_ATA 15 209#define MX3x_INT_UART3 18 210#define MX3x_INT_IIM 19 211#define MX3x_INT_RNGA 22 212#define MX3x_INT_EVTMON 23 213#define MX3x_INT_KPP 24 214#define MX3x_INT_RTC 25 215#define MX3x_INT_PWM 26 216#define MX3x_INT_EPIT2 27 217#define MX3x_INT_EPIT1 28 218#define MX3x_INT_GPT 29 219#define MX3x_INT_POWER_FAIL 30 220#define MX3x_INT_UART2 32 221#define MX3x_INT_NANDFC 33 222#define MX3x_INT_SDMA 34 223#define MX3x_INT_MSHC1 39 224#define MX3x_INT_IPU_ERR 41 225#define MX3x_INT_IPU_SYN 42 226#define MX3x_INT_UART1 45 227#define MX3x_INT_ECT 48 228#define MX3x_INT_SCC_SCM 49 229#define MX3x_INT_SCC_SMN 50 230#define MX3x_INT_GPIO2 51 231#define MX3x_INT_GPIO1 52 232#define MX3x_INT_WDOG 55 233#define MX3x_INT_GPIO3 56 234#define MX3x_INT_EXT_POWER 58 235#define MX3x_INT_EXT_TEMPER 59 236#define MX3x_INT_EXT_SENSOR60 60 237#define MX3x_INT_EXT_SENSOR61 61 238#define MX3x_INT_EXT_WDOG 62 239#define MX3x_INT_EXT_TV 63 240 241#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ 242 243/* silicon revisions specific to i.MX31 */ 244#define MX3x_CHIP_REV_1_0 0x10 245#define MX3x_CHIP_REV_1_1 0x11 246#define MX3x_CHIP_REV_1_2 0x12 247#define MX3x_CHIP_REV_1_3 0x13 248#define MX3x_CHIP_REV_2_0 0x20 249#define MX3x_CHIP_REV_2_1 0x21 250#define MX3x_CHIP_REV_2_2 0x22 251#define MX3x_CHIP_REV_2_3 0x23 252#define MX3x_CHIP_REV_3_0 0x30 253#define MX3x_CHIP_REV_3_1 0x31 254#define MX3x_CHIP_REV_3_2 0x32 255 256#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 257#define MX3x_SYSTEM_REV_NUM 3 258 259/* Mandatory defines used globally */ 260 261#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 262 263extern unsigned int mx31_cpu_rev; 264extern void mx31_read_cpu_rev(void); 265 266static inline int mx31_revision(void) 267{ 268 return mx31_cpu_rev; 269} 270#endif 271 272#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS 273/* these should go away */ 274#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR 275#define L2CC_SIZE MX3x_L2CC_SIZE 276#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR 277#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT 278#define AIPS1_SIZE MX3x_AIPS1_SIZE 279#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR 280#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR 281#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR 282#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR 283#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR 284#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR 285#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR 286#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR 287#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR 288#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR 289#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR 290#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR 291#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR 292#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR 293#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR 294#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR 295#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR 296#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR 297#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR 298#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT 299#define SPBA0_SIZE MX3x_SPBA0_SIZE 300#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR 301#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR 302#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR 303#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR 304#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR 305#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR 306#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR 307#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT 308#define AIPS2_SIZE MX3x_AIPS2_SIZE 309#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR 310#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR 311#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR 312#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR 313#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR 314#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR 315#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR 316#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR 317#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR 318#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR 319#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR 320#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR 321#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR 322#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR 323#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR 324#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR 325#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR 326#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT 327#define ROMP_SIZE MX3x_ROMP_SIZE 328#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR 329#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT 330#define AVIC_SIZE MX3x_AVIC_SIZE 331#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR 332#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR 333#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR 334#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR 335#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR 336#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR 337#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR 338#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR 339#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT 340#define CS4_SIZE MX3x_CS4_SIZE 341#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR 342#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT 343#define CS5_SIZE MX3x_CS5_SIZE 344#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR 345#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT 346#define X_MEMC_SIZE MX3x_X_MEMC_SIZE 347#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR 348#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR 349#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR 350#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR 351#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR 352#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR 353#define MXC_INT_I2C3 MX3x_INT_I2C3 354#define MXC_INT_I2C2 MX3x_INT_I2C2 355#define MXC_INT_RTIC MX3x_INT_RTIC 356#define MXC_INT_I2C MX3x_INT_I2C 357#define MXC_INT_CSPI2 MX3x_INT_CSPI2 358#define MXC_INT_CSPI1 MX3x_INT_CSPI1 359#define MXC_INT_ATA MX3x_INT_ATA 360#define MXC_INT_UART3 MX3x_INT_UART3 361#define MXC_INT_IIM MX3x_INT_IIM 362#define MXC_INT_RNGA MX3x_INT_RNGA 363#define MXC_INT_EVTMON MX3x_INT_EVTMON 364#define MXC_INT_KPP MX3x_INT_KPP 365#define MXC_INT_RTC MX3x_INT_RTC 366#define MXC_INT_PWM MX3x_INT_PWM 367#define MXC_INT_EPIT2 MX3x_INT_EPIT2 368#define MXC_INT_EPIT1 MX3x_INT_EPIT1 369#define MXC_INT_GPT MX3x_INT_GPT 370#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL 371#define MXC_INT_UART2 MX3x_INT_UART2 372#define MXC_INT_NANDFC MX3x_INT_NANDFC 373#define MXC_INT_SDMA MX3x_INT_SDMA 374#define MXC_INT_MSHC1 MX3x_INT_MSHC1 375#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR 376#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN 377#define MXC_INT_UART1 MX3x_INT_UART1 378#define MXC_INT_ECT MX3x_INT_ECT 379#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM 380#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN 381#define MXC_INT_GPIO2 MX3x_INT_GPIO2 382#define MXC_INT_GPIO1 MX3x_INT_GPIO1 383#define MXC_INT_WDOG MX3x_INT_WDOG 384#define MXC_INT_GPIO3 MX3x_INT_GPIO3 385#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER 386#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER 387#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60 388#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61 389#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG 390#define MXC_INT_EXT_TV MX3x_INT_EXT_TV 391#define PROD_SIGNATURE MX3x_PROD_SIGNATURE 392#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0 393#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1 394#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2 395#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3 396#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0 397#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1 398#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2 399#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3 400#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0 401#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1 402#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2 403#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN 404#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM 405#endif 406 407#endif /* ifndef __MACH_MX3x_H__ */ 408