1/* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 */ 4 5/* 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#ifndef __ASM_ARCH_MXC_IRQS_H__ 12#define __ASM_ARCH_MXC_IRQS_H__ 13 14/* 15 * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 16 */ 17#ifdef CONFIG_MXC_TZIC 18#define MXC_INTERNAL_IRQS 128 19#else 20#define MXC_INTERNAL_IRQS 64 21#endif 22 23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS 24 25/* these are ordered by size to support multi-SoC kernels */ 26#if defined CONFIG_ARCH_MX2 27#define MXC_GPIO_IRQS (32 * 6) 28#elif defined CONFIG_ARCH_MX1 29#define MXC_GPIO_IRQS (32 * 4) 30#elif defined CONFIG_ARCH_MX25 31#define MXC_GPIO_IRQS (32 * 4) 32#elif defined CONFIG_ARCH_MX5 33#define MXC_GPIO_IRQS (32 * 4) 34#elif defined CONFIG_ARCH_MXC91231 35#define MXC_GPIO_IRQS (32 * 4) 36#elif defined CONFIG_ARCH_MX3 37#define MXC_GPIO_IRQS (32 * 3) 38#endif 39 40/* 41 * The next 16 interrupts are for board specific purposes. Since 42 * the kernel can only run on one machine at a time, we can re-use 43 * these. If you need more, increase MXC_BOARD_IRQS, but keep it 44 * within sensible limits. 45 */ 46#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) 47 48#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 49#define MXC_BOARD_IRQS 80 50#else 51#define MXC_BOARD_IRQS 16 52#endif 53 54#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) 55 56#ifdef CONFIG_MX3_IPU_IRQS 57#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS 58#else 59#define MX3_IPU_IRQS 0 60#endif 61/* REVISIT: Add IPU irqs on IMX51 */ 62 63#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) 64 65extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); 66 67/* all normal IRQs can be FIQs */ 68#define FIQ_START 0 69/* switch betwean IRQ and FIQ */ 70extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); 71 72#endif /* __ASM_ARCH_MXC_IRQS_H__ */ 73