1/* 2 * Copyright (C) ST-Ericsson SA 2010 3 * 4 * License terms: GNU General Public License (GPL) version 2 5 */ 6 7#ifndef __MACH_DB8500_REGS_H 8#define __MACH_DB8500_REGS_H 9 10/* Base address and bank offsets for ESRAM */ 11#define U8500_ESRAM_BASE 0x40000000 12#define U8500_ESRAM_BANK_SIZE 0x00020000 13#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE 14#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE) 15#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE) 16#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE) 17#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE) 18/* Use bank 4 for DMA LCPA */ 19#define U8500_DMA_LCPA_BASE U8500_ESRAM_BANK4 20#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000) 21 22#define U8500_PER3_BASE 0x80000000 23#define U8500_STM_BASE 0x80100000 24#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000) 25#define U8500_PER2_BASE 0x80110000 26#define U8500_PER1_BASE 0x80120000 27#define U8500_B2R2_BASE 0x80130000 28#define U8500_HSEM_BASE 0x80140000 29#define U8500_PER4_BASE 0x80150000 30#define U8500_ICN_BASE 0x81000000 31 32#define U8500_BOOT_ROM_BASE 0x90000000 33/* ASIC ID is at 0xff4 offset within this region */ 34#define U8500_ASIC_ID_BASE 0x9001F000 35 36#define U8500_PER6_BASE 0xa03c0000 37#define U8500_PER5_BASE 0xa03e0000 38#define U8500_PER7_BASE_ED 0xa03d0000 39 40#define U8500_SVA_BASE 0xa0100000 41#define U8500_SIA_BASE 0xa0200000 42 43#define U8500_SGA_BASE 0xa0300000 44#define U8500_MCDE_BASE 0xa0350000 45#define U8500_DMA_BASE_ED 0xa0362000 46#define U8500_DMA_BASE 0x801C0000 /* v1 */ 47 48#define U8500_SBAG_BASE 0xa0390000 49 50#define U8500_SCU_BASE 0xa0410000 51#define U8500_GIC_CPU_BASE 0xa0410100 52#define U8500_TWD_BASE 0xa0410600 53#define U8500_GIC_DIST_BASE 0xa0411000 54#define U8500_L2CC_BASE 0xa0412000 55 56#define U8500_MODEM_I2C 0xb7e02000 57 58#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) 59#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000) 60#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) 61#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) 62 63/* per7 base addressess */ 64#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000) 65#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000) 66#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000) 67#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000) 68#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000) 69 70#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) 71#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) 72 73/* per6 base addressess */ 74#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) 75#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) 76#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) 77#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */ 78#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */ 79#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */ 80#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000) 81#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) 82#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) 83 84/* per5 base addressess */ 85#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) 86#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) 87 88/* per4 base addressess */ 89#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) 90#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) 91#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) 92#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000) 93#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000) 94#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) 95#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) 96#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) 97#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000) 98 99/* per3 base addresses */ 100#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) 101#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) 102#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000) 103#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000) 104#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000) 105#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000) 106#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) 107#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) 108#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) 109 110/* per2 base addressess */ 111#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) 112#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) 113#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) 114#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000) 115#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000) 116#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000) 117#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000) 118#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000) 119#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) 120#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000) 121#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000) 122#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) 123 124/* per1 base addresses */ 125#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) 126#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) 127#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) 128#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) 129#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) 130#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) 131#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000) 132#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000) 133#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) 134 135#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040 136 137#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE 138#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80) 139#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE 140#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80) 141#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100) 142#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180) 143#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE 144#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80) 145#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE 146 147#endif 148