1/* 2 * stmp378x: LCDIF register definitions 3 * 4 * Copyright (c) 2008 Freescale Semiconductor 5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000) 22#define REGS_LCDIF_PHYS 0x80030000 23#define REGS_LCDIF_SIZE 0x2000 24 25#define HW_LCDIF_CTRL 0x0 26#define BM_LCDIF_CTRL_RUN 0x00000001 27#define BP_LCDIF_CTRL_RUN 0 28#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020 29#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 30#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300 31#define BP_LCDIF_CTRL_WORD_LENGTH 8 32#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 33#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 34#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 35#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 36#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000 37#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000 38#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000 39#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000 40#define BM_LCDIF_CTRL_DVI_MODE 0x00100000 41#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 42#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 43#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 44#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 45#define BM_LCDIF_CTRL_CLKGATE 0x40000000 46#define BM_LCDIF_CTRL_SFTRST 0x80000000 47 48#define HW_LCDIF_CTRL1 0x10 49#define BM_LCDIF_CTRL1_RESET 0x00000001 50#define BP_LCDIF_CTRL1_RESET 0 51#define BM_LCDIF_CTRL1_MODE86 0x00000002 52#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 53#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 54#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 55#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 56#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 57#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 58#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 59#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 60#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 61#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000 62 63#define HW_LCDIF_TRANSFER_COUNT 0x20 64#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF 65#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 66#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 67#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16 68 69#define HW_LCDIF_CUR_BUF 0x30 70 71#define HW_LCDIF_NEXT_BUF 0x40 72 73#define HW_LCDIF_TIMING 0x60 74 75#define HW_LCDIF_VDCTRL0 0x70 76#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF 77#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 78#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 79#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 80#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 81#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 82#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 83#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 84#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 85#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 86 87#define HW_LCDIF_VDCTRL1 0x80 88#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF 89#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 90 91#define HW_LCDIF_VDCTRL2 0x90 92#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF 93#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 94#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000 95#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24 96 97#define HW_LCDIF_VDCTRL3 0xA0 98#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF 99#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 100#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 101#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 102 103#define HW_LCDIF_VDCTRL4 0xB0 104#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF 105#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 106#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000 107 108#define HW_LCDIF_DVICTRL0 0xC0 109#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF 110#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0 111#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00 112#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10 113#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000 114#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20 115 116#define HW_LCDIF_DVICTRL1 0xD0 117#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF 118#define BP_LCDIF_DVICTRL1_F2_START_LINE 0 119#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 120#define BP_LCDIF_DVICTRL1_F1_END_LINE 10 121#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 122#define BP_LCDIF_DVICTRL1_F1_START_LINE 20 123 124#define HW_LCDIF_DVICTRL2 0xE0 125#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF 126#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 127#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 128#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 129#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 130#define BP_LCDIF_DVICTRL2_F2_END_LINE 20 131 132#define HW_LCDIF_DVICTRL3 0xF0 133#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF 134#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0 135#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000 136#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16 137 138#define HW_LCDIF_DVICTRL4 0x100 139#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF 140#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 141#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 142#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 143#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 144#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 145#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 146#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24 147 148#define HW_LCDIF_CSC_COEFF0 0x110 149#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 150#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 151#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000 152#define BP_LCDIF_CSC_COEFF0_C0 16 153 154#define HW_LCDIF_CSC_COEFF1 0x120 155#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF 156#define BP_LCDIF_CSC_COEFF1_C1 0 157#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000 158#define BP_LCDIF_CSC_COEFF1_C2 16 159 160#define HW_LCDIF_CSC_COEFF2 0x130 161#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF 162#define BP_LCDIF_CSC_COEFF2_C3 0 163#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000 164#define BP_LCDIF_CSC_COEFF2_C4 16 165 166#define HW_LCDIF_CSC_COEFF3 0x140 167#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF 168#define BP_LCDIF_CSC_COEFF3_C5 0 169#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000 170#define BP_LCDIF_CSC_COEFF3_C6 16 171 172#define HW_LCDIF_CSC_COEFF4 0x150 173#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF 174#define BP_LCDIF_CSC_COEFF4_C7 0 175#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000 176#define BP_LCDIF_CSC_COEFF4_C8 16 177 178#define HW_LCDIF_CSC_OFFSET 0x160 179#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF 180#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 181#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 182#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16 183 184#define HW_LCDIF_CSC_LIMIT 0x170 185#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF 186#define BP_LCDIF_CSC_LIMIT_Y_MAX 0 187#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 188#define BP_LCDIF_CSC_LIMIT_Y_MIN 8 189#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 190#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 191#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 192#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24 193 194#define HW_LCDIF_STAT 0x1D0 195#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000 196