1/* 2 * sh7377 processor support - INTC hardware block 3 * 4 * Copyright (C) 2010 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 */ 19#include <linux/kernel.h> 20#include <linux/init.h> 21#include <linux/interrupt.h> 22#include <linux/irq.h> 23#include <linux/io.h> 24#include <linux/sh_intc.h> 25#include <asm/mach-types.h> 26#include <asm/mach/arch.h> 27 28enum { 29 UNUSED_INTCA = 0, 30 ENABLED, 31 DISABLED, 32 33 /* interrupt sources INTCA */ 34 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, 35 IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, 36 IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A, 37 IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A, 38 DIRC, 39 _2DG, 40 CRYPT_STD, 41 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, 42 AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX, 43 MFI_MFIM, MFI_MFIS, 44 BBIF1, BBIF2, 45 USBDMAC_USHDMI, 46 USBHS_USHI0, USBHS_USHI1, 47 _3DG_SGX540, 48 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, 49 KEYSC_KEY, 50 SCIFA0, SCIFA1, SCIFA2, SCIFA3, 51 MSIOF2, MSIOF1, 52 SCIFA4, SCIFA5, SCIFB, 53 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 54 SDHI0, 55 SDHI1, 56 MSU_MSU, MSU_MSU2, 57 IRREM, 58 MSUG, 59 IRDA, 60 TPU0, TPU1, TPU2, TPU3, TPU4, 61 LCRC, 62 PINTCA_PINT1, PINTCA_PINT2, 63 TTI20, 64 MISTY, 65 DDM, 66 RWDT0, RWDT1, 67 DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, 68 DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, 69 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, 70 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, 71 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, 72 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, 73 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 74 ICUSB_ICUSB0, ICUSB_ICUSB1, 75 ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, 76 SPU2_SPU0, SPU2_SPU1, 77 FSI, 78 FMSI, 79 SCUV, 80 IPMMU_IPMMUB, 81 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ, 82 MFIS2, 83 CPORTR2S, 84 CMT14, CMT15, 85 SCIFA6, 86 87 /* interrupt groups INTCA */ 88 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, 89 AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1, 90 ICUSB, ICUDMC 91}; 92 93static struct intc_vect intca_vectors[] __initdata = { 94 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), 95 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), 96 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), 97 INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), 98 INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), 99 INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), 100 INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), 101 INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), 102 INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220), 103 INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260), 104 INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0), 105 INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0), 106 INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320), 107 INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360), 108 INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0), 109 INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0), 110 INTC_VECT(DIRC, 0x0560), 111 INTC_VECT(_2DG, 0x05e0), 112 INTC_VECT(CRYPT_STD, 0x0700), 113 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), 114 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0), 115 INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840), 116 INTC_VECT(AP_ARM_COMMRX, 0x0860), 117 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), 118 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), 119 INTC_VECT(USBDMAC_USHDMI, 0x0a00), 120 INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40), 121 INTC_VECT(_3DG_SGX540, 0x0a60), 122 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), 123 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), 124 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0), 125 INTC_VECT(KEYSC_KEY, 0x0be0), 126 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20), 127 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60), 128 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00), 129 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40), 130 INTC_VECT(SCIFB, 0x0d60), 131 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), 132 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), 133 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20), 134 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60), 135 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0), 136 INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0), 137 INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40), 138 INTC_VECT(IRREM, 0x0f60), 139 INTC_VECT(MSUG, 0x0fa0), 140 INTC_VECT(IRDA, 0x0480), 141 INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0), 142 INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500), 143 INTC_VECT(TPU4, 0x0520), 144 INTC_VECT(LCRC, 0x0540), 145 INTC_VECT(PINTCA_PINT1, 0x1000), INTC_VECT(PINTCA_PINT2, 0x1020), 146 INTC_VECT(TTI20, 0x1100), 147 INTC_VECT(MISTY, 0x1120), 148 INTC_VECT(DDM, 0x1140), 149 INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0), 150 INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), 151 INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), 152 INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0), 153 INTC_VECT(DMAC_2_DADERR, 0x20c0), 154 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), 155 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), 156 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), 157 INTC_VECT(DMAC2_2_DADERR, 0x21c0), 158 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220), 159 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), 160 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), 161 INTC_VECT(DMAC3_2_DADERR, 0x22c0), 162 INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20), 163 INTC_VECT(SHWYSTAT_COM, 0x1340), 164 INTC_VECT(ICUSB_ICUSB0, 0x1700), INTC_VECT(ICUSB_ICUSB1, 0x1720), 165 INTC_VECT(ICUDMC_ICUDMC1, 0x1780), INTC_VECT(ICUDMC_ICUDMC2, 0x17a0), 166 INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820), 167 INTC_VECT(FSI, 0x1840), 168 INTC_VECT(FMSI, 0x1860), 169 INTC_VECT(SCUV, 0x1880), 170 INTC_VECT(IPMMU_IPMMUB, 0x1900), 171 INTC_VECT(AP_ARM_CTIIRQ, 0x1980), 172 INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0), 173 INTC_VECT(AP_ARM_DMAIRQ, 0x19c0), 174 INTC_VECT(AP_ARM_DMASIRQ, 0x19e0), 175 INTC_VECT(MFIS2, 0x1a00), 176 INTC_VECT(CPORTR2S, 0x1a20), 177 INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60), 178 INTC_VECT(SCIFA6, 0x1a80), 179}; 180 181static struct intc_group intca_groups[] __initdata = { 182 INTC_GROUP(DMAC_1, DMAC_1_DEI0, 183 DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3), 184 INTC_GROUP(DMAC_2, DMAC_2_DEI4, 185 DMAC_2_DEI5, DMAC_2_DADERR), 186 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, 187 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), 188 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, 189 DMAC2_2_DEI5, DMAC2_2_DADERR), 190 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0, 191 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), 192 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, 193 DMAC3_2_DEI5, DMAC3_2_DADERR), 194 INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX), 195 INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1), 196 INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), 197 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, 198 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 199 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), 200 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), 201 INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1), 202 INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2), 203}; 204 205static struct intc_mask_reg intca_mask_registers[] __initdata = { 206 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ 207 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 208 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ 209 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, 210 { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */ 211 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, 212 { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */ 213 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, 214 215 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ 216 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, 217 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, 218 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ 219 { _2DG, CRYPT_STD, DIRC, 0, 220 DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } }, 221 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ 222 { PINTCA_PINT1, PINTCA_PINT2, 0, 0, 223 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, 224 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */ 225 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, 226 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, 227 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */ 228 { DDM, 0, 0, 0, 229 0, 0, 0, 0 } }, 230 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ 231 { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4, 232 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, 233 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ 234 { SCIFB, SCIFA5, SCIFA4, MSIOF1, 235 0, 0, MSIOF2, 0 } }, 236 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ 237 { DISABLED, DISABLED, ENABLED, ENABLED, 238 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 239 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ 240 { DISABLED, DISABLED, ENABLED, ENABLED, 241 TTI20, USBDMAC_USHDMI, 0, MSUG } }, 242 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ 243 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, 244 CMT2, USBHS_USHI1, USBHS_USHI0, _3DG_SGX540 } }, 245 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */ 246 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, 247 0, 0, 0, 0 } }, 248 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */ 249 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1, 250 LCRC, MSU_MSU2, IRREM, MSU_MSU } }, 251 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */ 252 { 0, 0, TPU0, TPU1, 253 TPU2, TPU3, TPU4, 0 } }, 254 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ 255 { 0, 0, 0, 0, 256 MISTY, CMT3, RWDT1, RWDT0 } }, 257 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */ 258 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, 259 0, 0, 0, 0 } }, 260 { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */ 261 { ICUSB_ICUSB0, ICUSB_ICUSB1, 0, 0, 262 ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, 0, 0 } }, 263 { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */ 264 { SPU2_SPU0, SPU2_SPU1, FSI, FMSI, 265 SCUV, 0, 0, 0 } }, 266 { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */ 267 { IPMMU_IPMMUB, 0, 0, 0, 268 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, 269 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } }, 270 { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ 271 { MFIS2, CPORTR2S, CMT14, CMT15, 272 SCIFA6, 0, 0, 0 } }, 273}; 274 275static struct intc_prio_reg intca_prio_registers[] __initdata = { 276 { 0xe6900010, 0, 32, 4, /* INTPRI00A */ 277 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 278 { 0xe6900014, 0, 32, 4, /* INTPRI10A */ 279 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, 280 { 0xe6900018, 0, 32, 4, /* INTPRI10A */ 281 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, 282 { 0xe690001c, 0, 32, 4, /* INTPRI30A */ 283 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, 284 285 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, 286 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, 287 { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD, 288 CMT1_CMT11, AP_ARM1 } }, 289 { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINTCA_PINT1, PINTCA_PINT2, 290 CMT1_CMT12, TPU4 } }, 291 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS, 292 MFI_MFIM, USBHS } }, 293 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2, 294 _3DG_SGX540, CMT1_CMT10 } }, 295 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, 296 SCIFA2, SCIFA3 } }, 297 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI, 298 FLCTL, SDHI0 } }, 299 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } }, 300 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, MSUG, TTI20 } }, 301 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } }, 302 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } }, 303 { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } }, 304 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } }, 305 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, 0 } }, 306 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } }, 307 { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { ICUSB, 0, 0, 0 } }, 308 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { ICUDMC, 0, 0, 0 } }, 309 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, 310 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { SCUV, 0, 0, 0 } }, 311 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUB, 0, 0, 0 } }, 312 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, 313 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, 314 CMT14, CMT15 } }, 315 { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } }, 316}; 317 318static struct intc_sense_reg intca_sense_registers[] __initdata = { 319 { 0xe6900000, 16, 2, /* ICR1A */ 320 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 321 { 0xe6900004, 16, 2, /* ICR2A */ 322 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, 323 { 0xe6900008, 16, 2, /* ICR3A */ 324 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, 325 { 0xe690000c, 16, 2, /* ICR4A */ 326 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, 327}; 328 329static struct intc_mask_reg intca_ack_registers[] __initdata = { 330 { 0xe6900020, 0, 8, /* INTREQ00A */ 331 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 332 { 0xe6900024, 0, 8, /* INTREQ10A */ 333 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, 334 { 0xe6900028, 0, 8, /* INTREQ20A */ 335 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, 336 { 0xe690002c, 0, 8, /* INTREQ30A */ 337 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, 338}; 339 340static struct intc_desc intca_desc __initdata = { 341 .name = "sh7377-intca", 342 .force_enable = ENABLED, 343 .force_disable = DISABLED, 344 .hw = INTC_HW_DESC(intca_vectors, intca_groups, 345 intca_mask_registers, intca_prio_registers, 346 intca_sense_registers, intca_ack_registers), 347}; 348 349/* this macro ignore entry which is also in INTCA */ 350#define __IGNORE(a...) 351#define __IGNORE0(a...) 0 352 353enum { 354 UNUSED_INTCS = 0, 355 356 INTCS, 357 358 /* interrupt sources INTCS */ 359 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3, 360 RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3, 361 CEU, 362 BEU_BEU0, BEU_BEU1, BEU_BEU2, 363 __IGNORE(MFI) 364 __IGNORE(BBIF2) 365 VPU, 366 TSIF1, 367 __IGNORE(SGX540) 368 _2DDMAC, 369 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, 370 IPMMU_IPMMUR, IPMMU_IPMMUR2, 371 RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR, 372 __IGNORE(KEYSC) 373 __IGNORE(TTI20) 374 __IGNORE(MSIOF) 375 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0, 376 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, 377 CMT0, 378 TSIF0, 379 __IGNORE(CMT2) 380 LMB, 381 __IGNORE(MSUG) 382 __IGNORE(MSU_MSU, MSU_MSU2) 383 __IGNORE(CTI) 384 MVI3, 385 __IGNORE(RWDT0) 386 __IGNORE(RWDT1) 387 ICB, 388 PEP, 389 ASA, 390 __IGNORE(_2DG) 391 HQE, 392 JPU, 393 LCDC0, 394 __IGNORE(LCRC) 395 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3, 396 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 397 FRC, 398 LCDC1, 399 CSIRX, 400 DSITX_DSITX0, DSITX_DSITX1, 401 __IGNORE(SPU2_SPU0, SPU2_SPU1) 402 __IGNORE(FSI) 403 __IGNORE(FMSI) 404 __IGNORE(SCUV) 405 TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 406 TSIF2, 407 CMT4, 408 __IGNORE(MFIS2) 409 CPORTS2R, 410 411 /* interrupt groups INTCS */ 412 RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU, 413 IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1, 414}; 415 416#define INTCS_INTVECT 0x0F80 417static struct intc_vect intcs_vectors[] __initdata = { 418 INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720), 419 INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760), 420 INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820), 421 INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860), 422 INTCS_VECT(CEU, 0x0880), 423 INTCS_VECT(BEU_BEU0, 0x08A0), 424 INTCS_VECT(BEU_BEU1, 0x08C0), 425 INTCS_VECT(BEU_BEU2, 0x08E0), 426 __IGNORE(INTCS_VECT(MFI, 0x0900)) 427 __IGNORE(INTCS_VECT(BBIF2, 0x0960)) 428 INTCS_VECT(VPU, 0x0980), 429 INTCS_VECT(TSIF1, 0x09A0), 430 __IGNORE(INTCS_VECT(SGX540, 0x09E0)) 431 INTCS_VECT(_2DDMAC, 0x0A00), 432 INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0), 433 INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0), 434 INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20), 435 INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80), 436 INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0), 437 INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0), 438 __IGNORE(INTCS_VECT(KEYSC 0x0BE0)) 439 __IGNORE(INTCS_VECT(TTI20, 0x0C80)) 440 __IGNORE(INTCS_VECT(MSIOF, 0x0D20)) 441 INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20), 442 INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60), 443 INTCS_VECT(TMU_TUNI0, 0x0E80), 444 INTCS_VECT(TMU_TUNI1, 0x0EA0), 445 INTCS_VECT(TMU_TUNI2, 0x0EC0), 446 INTCS_VECT(CMT0, 0x0F00), 447 INTCS_VECT(TSIF0, 0x0F20), 448 __IGNORE(INTCS_VECT(CMT2, 0x0F40)) 449 INTCS_VECT(LMB, 0x0F60), 450 __IGNORE(INTCS_VECT(MSUG, 0x0F80)) 451 __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0)) 452 __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0)) 453 __IGNORE(INTCS_VECT(CTI, 0x0400)) 454 INTCS_VECT(MVI3, 0x0420), 455 __IGNORE(INTCS_VECT(RWDT0, 0x0440)) 456 __IGNORE(INTCS_VECT(RWDT1, 0x0460)) 457 INTCS_VECT(ICB, 0x0480), 458 INTCS_VECT(PEP, 0x04A0), 459 INTCS_VECT(ASA, 0x04C0), 460 __IGNORE(INTCS_VECT(_2DG, 0x04E0)) 461 INTCS_VECT(HQE, 0x0540), 462 INTCS_VECT(JPU, 0x0560), 463 INTCS_VECT(LCDC0, 0x0580), 464 __IGNORE(INTCS_VECT(LCRC, 0x05A0)) 465 INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320), 466 INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360), 467 INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0), 468 INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0), 469 INTCS_VECT(FRC, 0x1700), 470 INTCS_VECT(LCDC1, 0x1780), 471 INTCS_VECT(CSIRX, 0x17A0), 472 INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0), 473 __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800)) 474 __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820)) 475 __IGNORE(INTCS_VECT(FSI, 0x1840)) 476 __IGNORE(INTCS_VECT(FMSI, 0x1860)) 477 __IGNORE(INTCS_VECT(SCUV, 0x1880)) 478 INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920), 479 INTCS_VECT(TMU1_TUNI12, 0x1940), 480 INTCS_VECT(TSIF2, 0x1960), 481 INTCS_VECT(CMT4, 0x1980), 482 __IGNORE(INTCS_VECT(MFIS2, 0x1A00)) 483 INTCS_VECT(CPORTS2R, 0x1A20), 484 485 INTC_VECT(INTCS, INTCS_INTVECT), 486}; 487 488static struct intc_group intcs_groups[] __initdata = { 489 INTC_GROUP(RTDMAC1_1, 490 RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, 491 RTDMAC1_1_DEI2, RTDMAC1_1_DEI3), 492 INTC_GROUP(RTDMAC1_2, 493 RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR), 494 INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3), 495 INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2), 496 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0), 497 __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2)) 498 INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2), 499 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2), 500 INTC_GROUP(RTDMAC2_1, 501 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, 502 RTDMAC2_1_DEI2, RTDMAC2_1_DEI3), 503 INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR), 504 INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1), 505 __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1)) 506 INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12), 507}; 508 509static struct intc_mask_reg intcs_mask_registers[] __initdata = { 510 { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS */ 511 { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU, 512 VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } }, 513 { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */ 514 { 0, 0, 0, VPU, 515 __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } }, 516 { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */ 517 { 0, 0, 0, _2DDMAC, 518 __IGNORE0(_2DG), ASA, PEP, ICB } }, 519 { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */ 520 { 0, 0, MVI3, __IGNORE0(CTI), 521 JPU, HQE, __IGNORE0(LCRC), LCDC0 } }, 522 { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */ 523 { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4, 524 RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } }, 525 __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */ 526 { 0, 0, MSIOF, 0, 527 SGX540, 0, TTI20, 0 } }) 528 { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */ 529 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0, 530 0, 0, 0, 0 } }, 531 __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */ 532 { 0, 0, 0, 0, 533 0, MSU_MSU, MSU_MSU2, MSUG } }) 534 { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */ 535 { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0, 536 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } }, 537 { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */ 538 { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2, 539 0, 0, 0, 0 } }, 540 { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */ 541 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0, 542 0, TSIF1, LMB, TSIF0 } }, 543 { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */ 544 { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3, 545 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } }, 546 { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */ 547 { FRC, 0, 0, 0, 548 LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } }, 549 __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */ 550 {SPU2_SPU0, SPU2_SPU1, FSI, FMSI, 551 SCUV, 0, 0, 0 } }) 552 { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */ 553 { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2, 554 CMT4, 0, 0, 0 } }, 555 { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */ 556 { __IGNORE0(MFIS2), CPORTS2R, 0, 0, 557 0, 0, 0, 0 } }, 558 { 0xFFD20104, 0, 16, /* INTAMASK */ 559 { 0, 0, 0, 0, 0, 0, 0, 0, 560 0, 0, 0, 0, 0, 0, 0, INTCS } } 561}; 562 563static struct intc_prio_reg intcs_prio_registers[] __initdata = { 564 /* IPRAS */ 565 { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } }, 566 /* IPRBS */ 567 { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } }, 568 /* IPRCS */ 569 __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } }) 570 /* IPRES */ 571 { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } }, 572 /* IPRFS */ 573 { 0xFFD20014, 0, 16, 4, 574 { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } }, 575 /* IPRGS */ 576 { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } }, 577 /* IPRHS */ 578 { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } }, 579 /* IPRIS */ 580 { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } }, 581 /* IPRJS */ 582 __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } }) 583 /* IPRKS */ 584 { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } }, 585 /* IPRLS */ 586 { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } }, 587 /* IPRMS */ 588 { 0xFFD20030, 0, 16, 4, 589 { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } }, 590 /* IPRAS3 */ 591 { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } }, 592 /* IPRBS3 */ 593 { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } }, 594 /* IPRIS3 */ 595 { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } }, 596 /* IPRJS3 */ 597 { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } }, 598 /* IPRKS3 */ 599 __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } }) 600 /* IPRLS3 */ 601 __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } }) 602 /* IPRMS3 */ 603 { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } }, 604 /* IPRNS3 */ 605 { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } }, 606 /* IPROS3 */ 607 { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } }, 608}; 609 610static struct resource intcs_resources[] __initdata = { 611 [0] = { 612 .start = 0xffd20000, 613 .end = 0xffd500ff, 614 .flags = IORESOURCE_MEM, 615 } 616}; 617 618static struct intc_desc intcs_desc __initdata = { 619 .name = "sh7377-intcs", 620 .resource = intcs_resources, 621 .num_resources = ARRAY_SIZE(intcs_resources), 622 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, 623 intcs_mask_registers, intcs_prio_registers, 624 NULL, NULL), 625}; 626 627static void intcs_demux(unsigned int irq, struct irq_desc *desc) 628{ 629 void __iomem *reg = (void *)get_irq_data(irq); 630 unsigned int evtcodeas = ioread32(reg); 631 632 generic_handle_irq(intcs_evt2irq(evtcodeas)); 633} 634 635#define INTEVTSA 0xFFD20100 636void __init sh7377_init_irq(void) 637{ 638 void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE); 639 640 register_intc_controller(&intca_desc); 641 register_intc_controller(&intcs_desc); 642 643 /* demux using INTEVTSA */ 644 set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); 645 set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); 646} 647