1/* linux/arch/arm/plat-s3c64xx/dev-spi.c 2 * 3 * Copyright (C) 2009 Samsung Electronics Ltd. 4 * Jaswinder Singh <jassi.brar@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#include <linux/kernel.h> 12#include <linux/string.h> 13#include <linux/platform_device.h> 14#include <linux/dma-mapping.h> 15#include <linux/gpio.h> 16 17#include <mach/dma.h> 18#include <mach/map.h> 19#include <mach/gpio-bank-c.h> 20#include <mach/spi-clocks.h> 21#include <mach/irqs.h> 22 23#include <plat/s3c64xx-spi.h> 24#include <plat/gpio-cfg.h> 25#include <plat/devs.h> 26 27static char *spi_src_clks[] = { 28 [S3C64XX_SPI_SRCCLK_PCLK] = "pclk", 29 [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus", 30 [S3C64XX_SPI_SRCCLK_48M] = "spi_48m", 31}; 32 33/* SPI Controller platform_devices */ 34 35/* Since we emulate multi-cs capability, we do not touch the GPC-3,7. 36 * The emulated CS is toggled by board specific mechanism, as it can 37 * be either some immediate GPIO or some signal out of some other 38 * chip in between ... or some yet another way. 39 * We simply do not assume anything about CS. 40 */ 41static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev) 42{ 43 switch (pdev->id) { 44 case 0: 45 s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0); 46 s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLKO); 47 s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSIO); 48 s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_UP); 49 s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_UP); 50 s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_UP); 51 break; 52 53 case 1: 54 s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_SPI_MISO1); 55 s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_SPI_CLK1); 56 s3c_gpio_cfgpin(S3C64XX_GPC(6), S3C64XX_GPC6_SPI_MOSI1); 57 s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP); 58 s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP); 59 s3c_gpio_setpull(S3C64XX_GPC(6), S3C_GPIO_PULL_UP); 60 break; 61 62 default: 63 dev_err(&pdev->dev, "Invalid SPI Controller number!"); 64 return -EINVAL; 65 } 66 67 return 0; 68} 69 70static struct resource s3c64xx_spi0_resource[] = { 71 [0] = { 72 .start = S3C64XX_PA_SPI0, 73 .end = S3C64XX_PA_SPI0 + 0x100 - 1, 74 .flags = IORESOURCE_MEM, 75 }, 76 [1] = { 77 .start = DMACH_SPI0_TX, 78 .end = DMACH_SPI0_TX, 79 .flags = IORESOURCE_DMA, 80 }, 81 [2] = { 82 .start = DMACH_SPI0_RX, 83 .end = DMACH_SPI0_RX, 84 .flags = IORESOURCE_DMA, 85 }, 86 [3] = { 87 .start = IRQ_SPI0, 88 .end = IRQ_SPI0, 89 .flags = IORESOURCE_IRQ, 90 }, 91}; 92 93static struct s3c64xx_spi_info s3c64xx_spi0_pdata = { 94 .cfg_gpio = s3c64xx_spi_cfg_gpio, 95 .fifo_lvl_mask = 0x7f, 96 .rx_lvl_offset = 13, 97}; 98 99static u64 spi_dmamask = DMA_BIT_MASK(32); 100 101struct platform_device s3c64xx_device_spi0 = { 102 .name = "s3c64xx-spi", 103 .id = 0, 104 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource), 105 .resource = s3c64xx_spi0_resource, 106 .dev = { 107 .dma_mask = &spi_dmamask, 108 .coherent_dma_mask = DMA_BIT_MASK(32), 109 .platform_data = &s3c64xx_spi0_pdata, 110 }, 111}; 112EXPORT_SYMBOL(s3c64xx_device_spi0); 113 114static struct resource s3c64xx_spi1_resource[] = { 115 [0] = { 116 .start = S3C64XX_PA_SPI1, 117 .end = S3C64XX_PA_SPI1 + 0x100 - 1, 118 .flags = IORESOURCE_MEM, 119 }, 120 [1] = { 121 .start = DMACH_SPI1_TX, 122 .end = DMACH_SPI1_TX, 123 .flags = IORESOURCE_DMA, 124 }, 125 [2] = { 126 .start = DMACH_SPI1_RX, 127 .end = DMACH_SPI1_RX, 128 .flags = IORESOURCE_DMA, 129 }, 130 [3] = { 131 .start = IRQ_SPI1, 132 .end = IRQ_SPI1, 133 .flags = IORESOURCE_IRQ, 134 }, 135}; 136 137static struct s3c64xx_spi_info s3c64xx_spi1_pdata = { 138 .cfg_gpio = s3c64xx_spi_cfg_gpio, 139 .fifo_lvl_mask = 0x7f, 140 .rx_lvl_offset = 13, 141}; 142 143struct platform_device s3c64xx_device_spi1 = { 144 .name = "s3c64xx-spi", 145 .id = 1, 146 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource), 147 .resource = s3c64xx_spi1_resource, 148 .dev = { 149 .dma_mask = &spi_dmamask, 150 .coherent_dma_mask = DMA_BIT_MASK(32), 151 .platform_data = &s3c64xx_spi1_pdata, 152 }, 153}; 154EXPORT_SYMBOL(s3c64xx_device_spi1); 155 156void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) 157{ 158 struct s3c64xx_spi_info *pd; 159 160 /* Reject invalid configuration */ 161 if (!num_cs || src_clk_nr < 0 162 || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) { 163 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); 164 return; 165 } 166 167 switch (cntrlr) { 168 case 0: 169 pd = &s3c64xx_spi0_pdata; 170 break; 171 case 1: 172 pd = &s3c64xx_spi1_pdata; 173 break; 174 default: 175 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", 176 __func__, cntrlr); 177 return; 178 } 179 180 pd->num_cs = num_cs; 181 pd->src_clk_nr = src_clk_nr; 182 pd->src_clk_name = spi_src_clks[src_clk_nr]; 183} 184