1/* 2 * arch/arm/mach-orion5x/pci.c 3 * 4 * PCI and PCIe functions for Marvell Orion System On Chip 5 * 6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/pci.h> 15#include <linux/slab.h> 16#include <linux/mbus.h> 17#include <asm/irq.h> 18#include <asm/mach/pci.h> 19#include <plat/pcie.h> 20#include "common.h" 21 22/***************************************************************************** 23 * Orion has one PCIe controller and one PCI controller. 24 * 25 * Note1: The local PCIe bus number is '0'. The local PCI bus number 26 * follows the scanned PCIe bridged busses, if any. 27 * 28 * Note2: It is possible for PCI/PCIe agents to access many subsystem's 29 * space, by configuring BARs and Address Decode Windows, e.g. flashes on 30 * device bus, Orion registers, etc. However this code only enable the 31 * access to DDR banks. 32 ****************************************************************************/ 33 34 35/***************************************************************************** 36 * PCIe controller 37 ****************************************************************************/ 38#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) 39 40void __init orion5x_pcie_id(u32 *dev, u32 *rev) 41{ 42 *dev = orion_pcie_dev_id(PCIE_BASE); 43 *rev = orion_pcie_rev(PCIE_BASE); 44} 45 46static int pcie_valid_config(int bus, int dev) 47{ 48 /* 49 * Don't go out when trying to access -- 50 * 1. nonexisting device on local bus 51 * 2. where there's no device connected (no link) 52 */ 53 if (bus == 0 && dev == 0) 54 return 1; 55 56 if (!orion_pcie_link_up(PCIE_BASE)) 57 return 0; 58 59 if (bus == 0 && dev != 1) 60 return 0; 61 62 return 1; 63} 64 65 66/* 67 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register 68 * and then reading the PCIE_CONF_DATA register. Need to make sure these 69 * transactions are atomic. 70 */ 71static DEFINE_SPINLOCK(orion5x_pcie_lock); 72 73static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 74 int size, u32 *val) 75{ 76 unsigned long flags; 77 int ret; 78 79 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 80 *val = 0xffffffff; 81 return PCIBIOS_DEVICE_NOT_FOUND; 82 } 83 84 spin_lock_irqsave(&orion5x_pcie_lock, flags); 85 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); 86 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 87 88 return ret; 89} 90 91static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, 92 int where, int size, u32 *val) 93{ 94 int ret; 95 96 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 97 *val = 0xffffffff; 98 return PCIBIOS_DEVICE_NOT_FOUND; 99 } 100 101 /* 102 * We only support access to the non-extended configuration 103 * space when using the WA access method (or we would have to 104 * sacrifice 256M of CPU virtual address space.) 105 */ 106 if (where >= 0x100) { 107 *val = 0xffffffff; 108 return PCIBIOS_DEVICE_NOT_FOUND; 109 } 110 111 ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, 112 bus, devfn, where, size, val); 113 114 return ret; 115} 116 117static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 118 int where, int size, u32 val) 119{ 120 unsigned long flags; 121 int ret; 122 123 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) 124 return PCIBIOS_DEVICE_NOT_FOUND; 125 126 spin_lock_irqsave(&orion5x_pcie_lock, flags); 127 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); 128 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 129 130 return ret; 131} 132 133static struct pci_ops pcie_ops = { 134 .read = pcie_rd_conf, 135 .write = pcie_wr_conf, 136}; 137 138 139static int __init pcie_setup(struct pci_sys_data *sys) 140{ 141 struct resource *res; 142 int dev; 143 144 /* 145 * Generic PCIe unit setup. 146 */ 147 orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); 148 149 dev = orion_pcie_dev_id(PCIE_BASE); 150 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 151 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " 152 "read transaction workaround\n"); 153 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, 154 ORION5X_PCIE_WA_SIZE); 155 pcie_ops.read = pcie_rd_conf_wa; 156 } 157 158 /* 159 * Request resources. 160 */ 161 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 162 if (!res) 163 panic("pcie_setup unable to alloc resources"); 164 165 /* 166 * IORESOURCE_IO 167 */ 168 res[0].name = "PCIe I/O Space"; 169 res[0].flags = IORESOURCE_IO; 170 res[0].start = ORION5X_PCIE_IO_BUS_BASE; 171 res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; 172 if (request_resource(&ioport_resource, &res[0])) 173 panic("Request PCIe IO resource failed\n"); 174 sys->resource[0] = &res[0]; 175 176 /* 177 * IORESOURCE_MEM 178 */ 179 res[1].name = "PCIe Memory Space"; 180 res[1].flags = IORESOURCE_MEM; 181 res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; 182 res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; 183 if (request_resource(&iomem_resource, &res[1])) 184 panic("Request PCIe Memory resource failed\n"); 185 sys->resource[1] = &res[1]; 186 187 sys->resource[2] = NULL; 188 sys->io_offset = 0; 189 190 return 1; 191} 192 193/***************************************************************************** 194 * PCI controller 195 ****************************************************************************/ 196#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) 197#define PCI_MODE ORION5X_PCI_REG(0xd00) 198#define PCI_CMD ORION5X_PCI_REG(0xc00) 199#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) 200#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) 201#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) 202 203/* 204 * PCI_MODE bits 205 */ 206#define PCI_MODE_64BIT (1 << 2) 207#define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) 208 209/* 210 * PCI_CMD bits 211 */ 212#define PCI_CMD_HOST_REORDER (1 << 29) 213 214/* 215 * PCI_P2P_CONF bits 216 */ 217#define PCI_P2P_BUS_OFFS 16 218#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) 219#define PCI_P2P_DEV_OFFS 24 220#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) 221 222/* 223 * PCI_CONF_ADDR bits 224 */ 225#define PCI_CONF_REG(reg) ((reg) & 0xfc) 226#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) 227#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) 228#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) 229#define PCI_CONF_ADDR_EN (1 << 31) 230 231/* 232 * Internal configuration space 233 */ 234#define PCI_CONF_FUNC_STAT_CMD 0 235#define PCI_CONF_REG_STAT_CMD 4 236#define PCIX_STAT 0x64 237#define PCIX_STAT_BUS_OFFS 8 238#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) 239 240/* 241 * PCI Address Decode Windows registers 242 */ 243#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ 244 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ 245 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ 246 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) 247#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ 248 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ 249 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ 250 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) 251#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) 252#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) 253 254/* 255 * PCI configuration helpers for BAR settings 256 */ 257#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) 258#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) 259#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) 260 261/* 262 * PCI config cycles are done by programming the PCI_CONF_ADDR register 263 * and then reading the PCI_CONF_DATA register. Need to make sure these 264 * transactions are atomic. 265 */ 266static DEFINE_SPINLOCK(orion5x_pci_lock); 267 268static int orion5x_pci_cardbus_mode; 269 270static int orion5x_pci_local_bus_nr(void) 271{ 272 u32 conf = readl(PCI_P2P_CONF); 273 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); 274} 275 276static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, 277 u32 where, u32 size, u32 *val) 278{ 279 unsigned long flags; 280 spin_lock_irqsave(&orion5x_pci_lock, flags); 281 282 writel(PCI_CONF_BUS(bus) | 283 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 284 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 285 286 *val = readl(PCI_CONF_DATA); 287 288 if (size == 1) 289 *val = (*val >> (8*(where & 0x3))) & 0xff; 290 else if (size == 2) 291 *val = (*val >> (8*(where & 0x3))) & 0xffff; 292 293 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 294 295 return PCIBIOS_SUCCESSFUL; 296} 297 298static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, 299 u32 where, u32 size, u32 val) 300{ 301 unsigned long flags; 302 int ret = PCIBIOS_SUCCESSFUL; 303 304 spin_lock_irqsave(&orion5x_pci_lock, flags); 305 306 writel(PCI_CONF_BUS(bus) | 307 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 308 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 309 310 if (size == 4) { 311 __raw_writel(val, PCI_CONF_DATA); 312 } else if (size == 2) { 313 __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); 314 } else if (size == 1) { 315 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); 316 } else { 317 ret = PCIBIOS_BAD_REGISTER_NUMBER; 318 } 319 320 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 321 322 return ret; 323} 324 325static int orion5x_pci_valid_config(int bus, u32 devfn) 326{ 327 if (bus == orion5x_pci_local_bus_nr()) { 328 /* 329 * Don't go out for local device 330 */ 331 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) 332 return 0; 333 334 /* 335 * When the PCI signals are directly connected to a 336 * Cardbus slot, ignore all but device IDs 0 and 1. 337 */ 338 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) 339 return 0; 340 } 341 342 return 1; 343} 344 345static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, 346 int where, int size, u32 *val) 347{ 348 if (!orion5x_pci_valid_config(bus->number, devfn)) { 349 *val = 0xffffffff; 350 return PCIBIOS_DEVICE_NOT_FOUND; 351 } 352 353 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), 354 PCI_FUNC(devfn), where, size, val); 355} 356 357static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, 358 int where, int size, u32 val) 359{ 360 if (!orion5x_pci_valid_config(bus->number, devfn)) 361 return PCIBIOS_DEVICE_NOT_FOUND; 362 363 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), 364 PCI_FUNC(devfn), where, size, val); 365} 366 367static struct pci_ops pci_ops = { 368 .read = orion5x_pci_rd_conf, 369 .write = orion5x_pci_wr_conf, 370}; 371 372static void __init orion5x_pci_set_bus_nr(int nr) 373{ 374 u32 p2p = readl(PCI_P2P_CONF); 375 376 if (readl(PCI_MODE) & PCI_MODE_PCIX) { 377 /* 378 * PCI-X mode 379 */ 380 u32 pcix_status, bus, dev; 381 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; 382 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; 383 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); 384 pcix_status &= ~PCIX_STAT_BUS_MASK; 385 pcix_status |= (nr << PCIX_STAT_BUS_OFFS); 386 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); 387 } else { 388 /* 389 * PCI Conventional mode 390 */ 391 p2p &= ~PCI_P2P_BUS_MASK; 392 p2p |= (nr << PCI_P2P_BUS_OFFS); 393 writel(p2p, PCI_P2P_CONF); 394 } 395} 396 397static void __init orion5x_pci_master_slave_enable(void) 398{ 399 int bus_nr, func, reg; 400 u32 val; 401 402 bus_nr = orion5x_pci_local_bus_nr(); 403 func = PCI_CONF_FUNC_STAT_CMD; 404 reg = PCI_CONF_REG_STAT_CMD; 405 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); 406 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 407 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); 408} 409 410static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) 411{ 412 u32 win_enable; 413 int bus; 414 int i; 415 416 /* 417 * First, disable windows. 418 */ 419 win_enable = 0xffffffff; 420 writel(win_enable, PCI_BAR_ENABLE); 421 422 /* 423 * Setup windows for DDR banks. 424 */ 425 bus = orion5x_pci_local_bus_nr(); 426 427 for (i = 0; i < dram->num_cs; i++) { 428 struct mbus_dram_window *cs = dram->cs + i; 429 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); 430 u32 reg; 431 u32 val; 432 433 /* 434 * Write DRAM bank base address register. 435 */ 436 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); 437 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); 438 val = (cs->base & 0xfffff000) | (val & 0xfff); 439 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); 440 441 /* 442 * Write DRAM bank size register. 443 */ 444 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); 445 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); 446 writel((cs->size - 1) & 0xfffff000, 447 PCI_BAR_SIZE_DDR_CS(cs->cs_index)); 448 writel(cs->base & 0xfffff000, 449 PCI_BAR_REMAP_DDR_CS(cs->cs_index)); 450 451 /* 452 * Enable decode window for this chip select. 453 */ 454 win_enable &= ~(1 << cs->cs_index); 455 } 456 457 /* 458 * Re-enable decode windows. 459 */ 460 writel(win_enable, PCI_BAR_ENABLE); 461 462 /* 463 * Disable automatic update of address remapping when writing to BARs. 464 */ 465 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); 466} 467 468static int __init pci_setup(struct pci_sys_data *sys) 469{ 470 struct resource *res; 471 472 /* 473 * Point PCI unit MBUS decode windows to DRAM space. 474 */ 475 orion5x_setup_pci_wins(&orion5x_mbus_dram_info); 476 477 /* 478 * Master + Slave enable 479 */ 480 orion5x_pci_master_slave_enable(); 481 482 /* 483 * Force ordering 484 */ 485 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); 486 487 /* 488 * Request resources 489 */ 490 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 491 if (!res) 492 panic("pci_setup unable to alloc resources"); 493 494 /* 495 * IORESOURCE_IO 496 */ 497 res[0].name = "PCI I/O Space"; 498 res[0].flags = IORESOURCE_IO; 499 res[0].start = ORION5X_PCI_IO_BUS_BASE; 500 res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; 501 if (request_resource(&ioport_resource, &res[0])) 502 panic("Request PCI IO resource failed\n"); 503 sys->resource[0] = &res[0]; 504 505 /* 506 * IORESOURCE_MEM 507 */ 508 res[1].name = "PCI Memory Space"; 509 res[1].flags = IORESOURCE_MEM; 510 res[1].start = ORION5X_PCI_MEM_PHYS_BASE; 511 res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; 512 if (request_resource(&iomem_resource, &res[1])) 513 panic("Request PCI Memory resource failed\n"); 514 sys->resource[1] = &res[1]; 515 516 sys->resource[2] = NULL; 517 sys->io_offset = 0; 518 519 return 1; 520} 521 522 523/***************************************************************************** 524 * General PCIe + PCI 525 ****************************************************************************/ 526static void __devinit rc_pci_fixup(struct pci_dev *dev) 527{ 528 /* 529 * Prevent enumeration of root complex. 530 */ 531 if (dev->bus->parent == NULL && dev->devfn == 0) { 532 int i; 533 534 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 535 dev->resource[i].start = 0; 536 dev->resource[i].end = 0; 537 dev->resource[i].flags = 0; 538 } 539 } 540} 541DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); 542 543static int orion5x_pci_disabled __initdata; 544 545void __init orion5x_pci_disable(void) 546{ 547 orion5x_pci_disabled = 1; 548} 549 550void __init orion5x_pci_set_cardbus_mode(void) 551{ 552 orion5x_pci_cardbus_mode = 1; 553} 554 555int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) 556{ 557 int ret = 0; 558 559 if (nr == 0) { 560 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); 561 ret = pcie_setup(sys); 562 } else if (nr == 1 && !orion5x_pci_disabled) { 563 orion5x_pci_set_bus_nr(sys->busnr); 564 ret = pci_setup(sys); 565 } 566 567 return ret; 568} 569 570struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) 571{ 572 struct pci_bus *bus; 573 574 if (nr == 0) { 575 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 576 } else if (nr == 1 && !orion5x_pci_disabled) { 577 bus = pci_scan_bus(sys->busnr, &pci_ops, sys); 578 } else { 579 bus = NULL; 580 BUG(); 581 } 582 583 return bus; 584} 585 586int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 587{ 588 int bus = dev->bus->number; 589 590 /* 591 * PCIe endpoint? 592 */ 593 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) 594 return IRQ_ORION5X_PCIE0_INT; 595 596 return -1; 597} 598