1#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H 2#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H 3 4/* 5 * OMAP24XX Power/Reset Management register bits 6 * 7 * Copyright (C) 2007 Texas Instruments, Inc. 8 * Copyright (C) 2007 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17#include "prm.h" 18 19/* Bits shared between registers */ 20 21/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */ 22#define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2) 23#define OMAP24XX_WKUP2_ST_MASK (1 << 1) 24#define OMAP24XX_WKUP1_ST_MASK (1 << 0) 25 26/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */ 27#define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2) 28#define OMAP24XX_WKUP2_EN_MASK (1 << 1) 29#define OMAP24XX_WKUP1_EN_MASK (1 << 0) 30 31/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ 32#define OMAP24XX_EN_MPU_SHIFT 1 33#define OMAP24XX_EN_MPU_MASK (1 << 1) 34#define OMAP24XX_EN_CORE_SHIFT 0 35#define OMAP24XX_EN_CORE_MASK (1 << 0) 36 37/* 38 * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM 39 * shared bits 40 */ 41#define OMAP24XX_MEMONSTATE_SHIFT 10 42#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10) 43#define OMAP24XX_MEMRETSTATE_MASK (1 << 3) 44 45/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */ 46#define OMAP24XX_FORCESTATE_MASK (1 << 18) 47 48/* 49 * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP, 50 * PM_PWSTST_MDM shared bits 51 */ 52#define OMAP24XX_CLKACTIVITY_MASK (1 << 19) 53 54/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */ 55#define OMAP24XX_LASTSTATEENTERED_SHIFT 4 56#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4) 57 58/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */ 59#define OMAP2430_MEMSTATEST_SHIFT 10 60#define OMAP2430_MEMSTATEST_MASK (0x3 << 10) 61 62/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */ 63#define OMAP24XX_POWERSTATEST_SHIFT 0 64#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0) 65 66 67/* Bits specific to each register */ 68 69/* PRCM_REVISION */ 70#define OMAP24XX_REV_SHIFT 0 71#define OMAP24XX_REV_MASK (0xff << 0) 72 73/* PRCM_SYSCONFIG */ 74#define OMAP24XX_AUTOIDLE_MASK (1 << 0) 75 76/* PRCM_IRQSTATUS_MPU specific bits */ 77#define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6) 78#define OMAP24XX_TRANSITION_ST_MASK (1 << 5) 79#define OMAP24XX_EVGENOFF_ST_MASK (1 << 4) 80#define OMAP24XX_EVGENON_ST_MASK (1 << 3) 81 82/* PRCM_IRQENABLE_MPU specific bits */ 83#define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6) 84#define OMAP24XX_TRANSITION_EN_MASK (1 << 5) 85#define OMAP24XX_EVGENOFF_EN_MASK (1 << 4) 86#define OMAP24XX_EVGENON_EN_MASK (1 << 3) 87 88/* PRCM_VOLTCTRL */ 89#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15) 90#define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14) 91#define OMAP24XX_SETOFF_LEVEL_SHIFT 12 92#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12) 93#define OMAP24XX_MEMRETCTRL_MASK (1 << 8) 94#define OMAP24XX_SETRET_LEVEL_SHIFT 6 95#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6) 96#define OMAP24XX_VOLT_LEVEL_SHIFT 0 97#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0) 98 99/* PRCM_VOLTST */ 100#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0 101#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0) 102 103/* PRCM_CLKSRC_CTRL specific bits */ 104 105/* PRCM_CLKOUT_CTRL */ 106#define OMAP2420_CLKOUT2_EN_SHIFT 15 107#define OMAP2420_CLKOUT2_EN_MASK (1 << 15) 108#define OMAP2420_CLKOUT2_DIV_SHIFT 11 109#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) 110#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 111#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) 112#define OMAP24XX_CLKOUT_EN_SHIFT 7 113#define OMAP24XX_CLKOUT_EN_MASK (1 << 7) 114#define OMAP24XX_CLKOUT_DIV_SHIFT 3 115#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) 116#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 117#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) 118 119/* PRCM_CLKEMUL_CTRL */ 120#define OMAP24XX_EMULATION_EN_SHIFT 0 121#define OMAP24XX_EMULATION_EN_MASK (1 << 0) 122 123/* PRCM_CLKCFG_CTRL */ 124#define OMAP24XX_VALID_CONFIG_MASK (1 << 0) 125 126/* PRCM_CLKCFG_STATUS */ 127#define OMAP24XX_CONFIG_STATUS_MASK (1 << 0) 128 129/* PRCM_VOLTSETUP specific bits */ 130 131/* PRCM_CLKSSETUP specific bits */ 132 133/* PRCM_POLCTRL */ 134#define OMAP2420_CLKOUT2_POL_MASK (1 << 10) 135#define OMAP24XX_CLKOUT_POL_MASK (1 << 9) 136#define OMAP24XX_CLKREQ_POL_MASK (1 << 8) 137#define OMAP2430_USE_POWEROK_MASK (1 << 2) 138#define OMAP2430_POWEROK_POL_MASK (1 << 1) 139#define OMAP24XX_EXTVOL_POL_MASK (1 << 0) 140 141/* RM_RSTST_MPU specific bits */ 142/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ 143 144/* PM_WKDEP_MPU specific bits */ 145#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5 146#define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5) 147#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2 148#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2) 149 150/* PM_EVGENCTRL_MPU specific bits */ 151 152/* PM_EVEGENONTIM_MPU specific bits */ 153 154/* PM_EVEGENOFFTIM_MPU specific bits */ 155 156/* PM_PWSTCTRL_MPU specific bits */ 157#define OMAP2430_FORCESTATE_MASK (1 << 18) 158 159/* PM_PWSTST_MPU specific bits */ 160/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */ 161 162/* PM_WKEN1_CORE specific bits */ 163 164/* PM_WKEN2_CORE specific bits */ 165 166/* PM_WKST1_CORE specific bits*/ 167 168/* PM_WKST2_CORE specific bits */ 169 170/* PM_WKDEP_CORE specific bits*/ 171#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5) 172#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3) 173#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2) 174 175/* PM_PWSTCTRL_CORE specific bits */ 176#define OMAP24XX_MEMORYCHANGE_MASK (1 << 20) 177#define OMAP24XX_MEM3ONSTATE_SHIFT 14 178#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14) 179#define OMAP24XX_MEM2ONSTATE_SHIFT 12 180#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12) 181#define OMAP24XX_MEM1ONSTATE_SHIFT 10 182#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10) 183#define OMAP24XX_MEM3RETSTATE_MASK (1 << 5) 184#define OMAP24XX_MEM2RETSTATE_MASK (1 << 4) 185#define OMAP24XX_MEM1RETSTATE_MASK (1 << 3) 186 187/* PM_PWSTST_CORE specific bits */ 188#define OMAP24XX_MEM3STATEST_SHIFT 14 189#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14) 190#define OMAP24XX_MEM2STATEST_SHIFT 12 191#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12) 192#define OMAP24XX_MEM1STATEST_SHIFT 10 193#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10) 194 195/* RM_RSTCTRL_GFX */ 196#define OMAP24XX_GFX_RST_MASK (1 << 0) 197 198/* RM_RSTST_GFX specific bits */ 199#define OMAP24XX_GFX_SW_RST_MASK (1 << 4) 200 201/* PM_PWSTCTRL_GFX specific bits */ 202 203/* PM_WKDEP_GFX specific bits */ 204/* 2430 often calls EN_WAKEUP "EN_WKUP" */ 205 206/* RM_RSTCTRL_WKUP specific bits */ 207 208/* RM_RSTTIME_WKUP specific bits */ 209 210/* RM_RSTST_WKUP specific bits */ 211/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */ 212#define OMAP24XX_EXTWMPU_RST_MASK (1 << 6) 213#define OMAP24XX_SECU_WD_RST_MASK (1 << 5) 214#define OMAP24XX_MPU_WD_RST_MASK (1 << 4) 215#define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3) 216 217/* PM_WKEN_WKUP specific bits */ 218 219/* PM_WKST_WKUP specific bits */ 220 221/* RM_RSTCTRL_DSP */ 222#define OMAP2420_RST_IVA_MASK (1 << 8) 223#define OMAP24XX_RST2_DSP_MASK (1 << 1) 224#define OMAP24XX_RST1_DSP_MASK (1 << 0) 225 226/* RM_RSTST_DSP specific bits */ 227/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */ 228#define OMAP2420_IVA_SW_RST_MASK (1 << 8) 229#define OMAP24XX_DSP_SW_RST2_MASK (1 << 5) 230#define OMAP24XX_DSP_SW_RST1_MASK (1 << 4) 231 232/* PM_WKDEP_DSP specific bits */ 233 234/* PM_PWSTCTRL_DSP specific bits */ 235/* 2430 only: MEMONSTATE, MEMRETSTATE */ 236#define OMAP2420_MEMIONSTATE_SHIFT 12 237#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12) 238#define OMAP2420_MEMIRETSTATE_MASK (1 << 4) 239 240/* PM_PWSTST_DSP specific bits */ 241/* MEMSTATEST is 2430 only */ 242#define OMAP2420_MEMISTATEST_SHIFT 12 243#define OMAP2420_MEMISTATEST_MASK (0x3 << 12) 244 245/* PRCM_IRQSTATUS_DSP specific bits */ 246 247/* PRCM_IRQENABLE_DSP specific bits */ 248 249/* RM_RSTCTRL_MDM */ 250/* 2430 only */ 251#define OMAP2430_PWRON1_MDM_MASK (1 << 1) 252#define OMAP2430_RST1_MDM_MASK (1 << 0) 253 254/* RM_RSTST_MDM specific bits */ 255/* 2430 only */ 256#define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6) 257#define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5) 258#define OMAP2430_MDM_SW_RST1_MASK (1 << 4) 259 260/* PM_WKEN_MDM */ 261/* 2430 only */ 262#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0) 263 264/* PM_WKST_MDM specific bits */ 265/* 2430 only */ 266 267/* PM_WKDEP_MDM specific bits */ 268/* 2430 only */ 269 270/* PM_PWSTCTRL_MDM specific bits */ 271/* 2430 only */ 272#define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19) 273 274/* PM_PWSTST_MDM specific bits */ 275/* 2430 only */ 276 277/* PRCM_IRQSTATUS_IVA */ 278/* 2420 only */ 279 280/* PRCM_IRQENABLE_IVA */ 281/* 2420 only */ 282 283#endif 284