1/* 2 * Copyright (C) 2009 Sascha Hauer, Pengutronix 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15#include <linux/types.h> 16#include <linux/init.h> 17 18#include <linux/platform_device.h> 19#include <linux/mtd/physmap.h> 20#include <linux/mtd/plat-ram.h> 21#include <linux/memory.h> 22#include <linux/gpio.h> 23#include <linux/smc911x.h> 24#include <linux/interrupt.h> 25#include <linux/delay.h> 26#include <linux/i2c.h> 27#include <linux/i2c/at24.h> 28#include <linux/usb/otg.h> 29#include <linux/usb/ulpi.h> 30#include <linux/fsl_devices.h> 31 32#include <asm/mach-types.h> 33#include <asm/mach/arch.h> 34#include <asm/mach/time.h> 35#include <asm/mach/map.h> 36 37#include <mach/hardware.h> 38#include <mach/common.h> 39#include <mach/iomux-mx35.h> 40#include <mach/ipu.h> 41#include <mach/mx3fb.h> 42#include <mach/mxc_ehci.h> 43#include <mach/ulpi.h> 44#include <mach/audmux.h> 45#include <mach/ssi.h> 46 47#include "devices-imx35.h" 48#include "devices.h" 49 50static const struct fb_videomode fb_modedb[] = { 51 { 52 /* 240x320 @ 60 Hz */ 53 .name = "Sharp-LQ035Q7", 54 .refresh = 60, 55 .xres = 240, 56 .yres = 320, 57 .pixclock = 185925, 58 .left_margin = 9, 59 .right_margin = 16, 60 .upper_margin = 7, 61 .lower_margin = 9, 62 .hsync_len = 1, 63 .vsync_len = 1, 64 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, 65 .vmode = FB_VMODE_NONINTERLACED, 66 .flag = 0, 67 }, { 68 /* 240x320 @ 60 Hz */ 69 .name = "TX090", 70 .refresh = 60, 71 .xres = 240, 72 .yres = 320, 73 .pixclock = 38255, 74 .left_margin = 144, 75 .right_margin = 0, 76 .upper_margin = 7, 77 .lower_margin = 40, 78 .hsync_len = 96, 79 .vsync_len = 1, 80 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, 81 .vmode = FB_VMODE_NONINTERLACED, 82 .flag = 0, 83 }, 84}; 85 86static struct ipu_platform_data mx3_ipu_data = { 87 .irq_base = MXC_IPU_IRQ_START, 88}; 89 90static struct mx3fb_platform_data mx3fb_pdata = { 91 .dma_dev = &mx3_ipu.dev, 92 .name = "Sharp-LQ035Q7", 93 .mode = fb_modedb, 94 .num_modes = ARRAY_SIZE(fb_modedb), 95}; 96 97static struct physmap_flash_data pcm043_flash_data = { 98 .width = 2, 99}; 100 101static struct resource pcm043_flash_resource = { 102 .start = 0xa0000000, 103 .end = 0xa1ffffff, 104 .flags = IORESOURCE_MEM, 105}; 106 107static struct platform_device pcm043_flash = { 108 .name = "physmap-flash", 109 .id = 0, 110 .dev = { 111 .platform_data = &pcm043_flash_data, 112 }, 113 .resource = &pcm043_flash_resource, 114 .num_resources = 1, 115}; 116 117static const struct imxuart_platform_data uart_pdata __initconst = { 118 .flags = IMXUART_HAVE_RTSCTS, 119}; 120 121#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE 122static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = { 123 .bitrate = 50000, 124}; 125 126static struct at24_platform_data board_eeprom = { 127 .byte_len = 4096, 128 .page_size = 32, 129 .flags = AT24_FLAG_ADDR16, 130}; 131 132static struct i2c_board_info pcm043_i2c_devices[] = { 133 { 134 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ 135 .platform_data = &board_eeprom, 136 }, { 137 I2C_BOARD_INFO("pcf8563", 0x51), 138 } 139}; 140#endif 141 142static struct platform_device *devices[] __initdata = { 143 &pcm043_flash, 144 &mxc_fec_device, 145 &imx_wdt_device0, 146}; 147 148static struct pad_desc pcm043_pads[] = { 149 /* UART1 */ 150 MX35_PAD_CTS1__UART1_CTS, 151 MX35_PAD_RTS1__UART1_RTS, 152 MX35_PAD_TXD1__UART1_TXD_MUX, 153 MX35_PAD_RXD1__UART1_RXD_MUX, 154 /* UART2 */ 155 MX35_PAD_CTS2__UART2_CTS, 156 MX35_PAD_RTS2__UART2_RTS, 157 MX35_PAD_TXD2__UART2_TXD_MUX, 158 MX35_PAD_RXD2__UART2_RXD_MUX, 159 /* FEC */ 160 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, 161 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, 162 MX35_PAD_FEC_RX_DV__FEC_RX_DV, 163 MX35_PAD_FEC_COL__FEC_COL, 164 MX35_PAD_FEC_RDATA0__FEC_RDATA_0, 165 MX35_PAD_FEC_TDATA0__FEC_TDATA_0, 166 MX35_PAD_FEC_TX_EN__FEC_TX_EN, 167 MX35_PAD_FEC_MDC__FEC_MDC, 168 MX35_PAD_FEC_MDIO__FEC_MDIO, 169 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, 170 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, 171 MX35_PAD_FEC_CRS__FEC_CRS, 172 MX35_PAD_FEC_RDATA1__FEC_RDATA_1, 173 MX35_PAD_FEC_TDATA1__FEC_TDATA_1, 174 MX35_PAD_FEC_RDATA2__FEC_RDATA_2, 175 MX35_PAD_FEC_TDATA2__FEC_TDATA_2, 176 MX35_PAD_FEC_RDATA3__FEC_RDATA_3, 177 MX35_PAD_FEC_TDATA3__FEC_TDATA_3, 178 /* I2C1 */ 179 MX35_PAD_I2C1_CLK__I2C1_SCL, 180 MX35_PAD_I2C1_DAT__I2C1_SDA, 181 /* Display */ 182 MX35_PAD_LD0__IPU_DISPB_DAT_0, 183 MX35_PAD_LD1__IPU_DISPB_DAT_1, 184 MX35_PAD_LD2__IPU_DISPB_DAT_2, 185 MX35_PAD_LD3__IPU_DISPB_DAT_3, 186 MX35_PAD_LD4__IPU_DISPB_DAT_4, 187 MX35_PAD_LD5__IPU_DISPB_DAT_5, 188 MX35_PAD_LD6__IPU_DISPB_DAT_6, 189 MX35_PAD_LD7__IPU_DISPB_DAT_7, 190 MX35_PAD_LD8__IPU_DISPB_DAT_8, 191 MX35_PAD_LD9__IPU_DISPB_DAT_9, 192 MX35_PAD_LD10__IPU_DISPB_DAT_10, 193 MX35_PAD_LD11__IPU_DISPB_DAT_11, 194 MX35_PAD_LD12__IPU_DISPB_DAT_12, 195 MX35_PAD_LD13__IPU_DISPB_DAT_13, 196 MX35_PAD_LD14__IPU_DISPB_DAT_14, 197 MX35_PAD_LD15__IPU_DISPB_DAT_15, 198 MX35_PAD_LD16__IPU_DISPB_DAT_16, 199 MX35_PAD_LD17__IPU_DISPB_DAT_17, 200 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, 201 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, 202 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, 203 MX35_PAD_CONTRAST__IPU_DISPB_CONTR, 204 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, 205 MX35_PAD_D3_REV__IPU_DISPB_D3_REV, 206 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, 207 /* gpio */ 208 MX35_PAD_ATA_CS0__GPIO2_6, 209 /* USB host */ 210 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, 211 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, 212 /* SSI */ 213 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, 214 MX35_PAD_STXD4__AUDMUX_AUD4_TXD, 215 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, 216 MX35_PAD_SCK4__AUDMUX_AUD4_TXC, 217 /* CAN2 */ 218 MX35_PAD_TX5_RX0__CAN2_TXCAN, 219 MX35_PAD_TX4_RX1__CAN2_RXCAN, 220}; 221 222#define AC97_GPIO_TXFS (1 * 32 + 31) 223#define AC97_GPIO_TXD (1 * 32 + 28) 224#define AC97_GPIO_RESET (1 * 32 + 0) 225 226static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) 227{ 228 struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; 229 struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; 230 int ret; 231 232 ret = gpio_request(AC97_GPIO_TXFS, "SSI"); 233 if (ret) { 234 printk("failed to get GPIO_TXFS: %d\n", ret); 235 return; 236 } 237 238 mxc_iomux_v3_setup_pad(&txfs_gpio); 239 240 /* warm reset */ 241 gpio_direction_output(AC97_GPIO_TXFS, 1); 242 udelay(2); 243 gpio_set_value(AC97_GPIO_TXFS, 0); 244 245 gpio_free(AC97_GPIO_TXFS); 246 mxc_iomux_v3_setup_pad(&txfs); 247} 248 249static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) 250{ 251 struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; 252 struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; 253 struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28; 254 struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; 255 struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; 256 int ret; 257 258 ret = gpio_request(AC97_GPIO_TXFS, "SSI"); 259 if (ret) 260 goto err1; 261 262 ret = gpio_request(AC97_GPIO_TXD, "SSI"); 263 if (ret) 264 goto err2; 265 266 ret = gpio_request(AC97_GPIO_RESET, "SSI"); 267 if (ret) 268 goto err3; 269 270 mxc_iomux_v3_setup_pad(&txfs_gpio); 271 mxc_iomux_v3_setup_pad(&txd_gpio); 272 mxc_iomux_v3_setup_pad(&reset_gpio); 273 274 gpio_direction_output(AC97_GPIO_TXFS, 0); 275 gpio_direction_output(AC97_GPIO_TXD, 0); 276 277 /* cold reset */ 278 gpio_direction_output(AC97_GPIO_RESET, 0); 279 udelay(10); 280 gpio_direction_output(AC97_GPIO_RESET, 1); 281 282 mxc_iomux_v3_setup_pad(&txd); 283 mxc_iomux_v3_setup_pad(&txfs); 284 285 gpio_free(AC97_GPIO_RESET); 286err3: 287 gpio_free(AC97_GPIO_TXD); 288err2: 289 gpio_free(AC97_GPIO_TXFS); 290err1: 291 if (ret) 292 printk("%s failed with %d\n", __func__, ret); 293 mdelay(1); 294} 295 296static struct imx_ssi_platform_data pcm043_ssi_pdata = { 297 .ac97_reset = pcm043_ac97_cold_reset, 298 .ac97_warm_reset = pcm043_ac97_warm_reset, 299 .flags = IMX_SSI_USE_AC97, 300}; 301 302static const struct mxc_nand_platform_data 303pcm037_nand_board_info __initconst = { 304 .width = 1, 305 .hw_ecc = 1, 306}; 307 308#if defined(CONFIG_USB_ULPI) 309static struct mxc_usbh_platform_data otg_pdata = { 310 .portsc = MXC_EHCI_MODE_UTMI, 311 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 312}; 313 314static struct mxc_usbh_platform_data usbh1_pdata = { 315 .portsc = MXC_EHCI_MODE_SERIAL, 316 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | 317 MXC_EHCI_IPPUE_DOWN, 318}; 319#endif 320 321static struct fsl_usb2_platform_data otg_device_pdata = { 322 .operating_mode = FSL_USB2_DR_DEVICE, 323 .phy_mode = FSL_USB2_PHY_UTMI, 324}; 325 326static int otg_mode_host; 327 328static int __init pcm043_otg_mode(char *options) 329{ 330 if (!strcmp(options, "host")) 331 otg_mode_host = 1; 332 else if (!strcmp(options, "device")) 333 otg_mode_host = 0; 334 else 335 pr_info("otg_mode neither \"host\" nor \"device\". " 336 "Defaulting to device\n"); 337 return 0; 338} 339__setup("otg_mode=", pcm043_otg_mode); 340 341/* 342 * Board specific initialization. 343 */ 344static void __init mxc_board_init(void) 345{ 346 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); 347 348 mxc_audmux_v2_configure_port(3, 349 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ 350 MXC_AUDMUX_V2_PTCR_TFSEL(0) | 351 MXC_AUDMUX_V2_PTCR_TFSDIR, 352 MXC_AUDMUX_V2_PDCR_RXDSEL(0)); 353 354 mxc_audmux_v2_configure_port(0, 355 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ 356 MXC_AUDMUX_V2_PTCR_TCSEL(3) | 357 MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */ 358 MXC_AUDMUX_V2_PDCR_RXDSEL(3)); 359 360 platform_add_devices(devices, ARRAY_SIZE(devices)); 361 362 imx35_add_imx_uart0(&uart_pdata); 363 imx35_add_mxc_nand(&pcm037_nand_board_info); 364 mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata); 365 366 imx35_add_imx_uart1(&uart_pdata); 367 368#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE 369 i2c_register_board_info(0, pcm043_i2c_devices, 370 ARRAY_SIZE(pcm043_i2c_devices)); 371 372 imx35_add_imx_i2c0(&pcm043_i2c0_data); 373#endif 374 375 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 376 mxc_register_device(&mx3_fb, &mx3fb_pdata); 377 378#if defined(CONFIG_USB_ULPI) 379 if (otg_mode_host) { 380 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 381 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 382 383 mxc_register_device(&mxc_otg_host, &otg_pdata); 384 } 385 386 mxc_register_device(&mxc_usbh1, &usbh1_pdata); 387#endif 388 if (!otg_mode_host) 389 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 390 391 imx35_add_flexcan1(NULL); 392} 393 394static void __init pcm043_timer_init(void) 395{ 396 mx35_clocks_init(); 397} 398 399struct sys_timer pcm043_timer = { 400 .init = pcm043_timer_init, 401}; 402 403MACHINE_START(PCM043, "Phytec Phycore pcm043") 404 /* Maintainer: Pengutronix */ 405 .phys_io = MX35_AIPS1_BASE_ADDR, 406 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 407 .boot_params = MX3x_PHYS_OFFSET + 0x100, 408 .map_io = mx35_map_io, 409 .init_irq = mx35_init_irq, 410 .init_machine = mxc_board_init, 411 .timer = &pcm043_timer, 412MACHINE_END 413