1/* 2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15#include <linux/delay.h> 16#include <linux/types.h> 17#include <linux/init.h> 18#include <linux/clk.h> 19#include <linux/irq.h> 20#include <linux/gpio.h> 21#include <linux/platform_device.h> 22#include <linux/mfd/mc13783.h> 23#include <linux/spi/spi.h> 24#include <linux/regulator/machine.h> 25#include <linux/fsl_devices.h> 26#include <linux/input/matrix_keypad.h> 27 28#include <mach/hardware.h> 29#include <asm/mach-types.h> 30#include <asm/mach/arch.h> 31#include <asm/mach/time.h> 32#include <asm/memory.h> 33#include <asm/mach/map.h> 34#include <mach/common.h> 35#include <mach/iomux-mx3.h> 36#include <mach/3ds_debugboard.h> 37 38#include "devices-imx31.h" 39#include "devices.h" 40 41/* Definitions for components on the Debug board */ 42 43/* Base address of CPLD controller on the Debug board */ 44#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR) 45 46/* LAN9217 ethernet base address */ 47#define LAN9217_BASE_ADDR MX3x_CS5_BASE_ADDR 48 49/* CPLD config and interrupt base address */ 50#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000) 51 52/* status, interrupt */ 53#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10) 54#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38) 55#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20) 56/* magic word for debug CPLD */ 57#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40) 58#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48) 59/* CPLD code version */ 60#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50) 61/* magic word for debug CPLD */ 62#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58) 63 64/* CPLD IRQ line for external uart, external ethernet etc */ 65#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) 66 67#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) 68#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) 69 70#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0) 71 72#define MXC_MAX_EXP_IO_LINES 16 73 74/* 75 * This file contains the board-specific initialization routines. 76 */ 77 78static int mx31_3ds_pins[] = { 79 /* UART1 */ 80 MX31_PIN_CTS1__CTS1, 81 MX31_PIN_RTS1__RTS1, 82 MX31_PIN_TXD1__TXD1, 83 MX31_PIN_RXD1__RXD1, 84 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), 85 /* SPI 1 */ 86 MX31_PIN_CSPI2_SCLK__SCLK, 87 MX31_PIN_CSPI2_MOSI__MOSI, 88 MX31_PIN_CSPI2_MISO__MISO, 89 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, 90 MX31_PIN_CSPI2_SS0__SS0, 91 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ 92 /* MC13783 IRQ */ 93 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), 94 /* USB OTG reset */ 95 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO), 96 /* USB OTG */ 97 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, 98 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, 99 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, 100 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, 101 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, 102 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, 103 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, 104 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, 105 MX31_PIN_USBOTG_CLK__USBOTG_CLK, 106 MX31_PIN_USBOTG_DIR__USBOTG_DIR, 107 MX31_PIN_USBOTG_NXT__USBOTG_NXT, 108 MX31_PIN_USBOTG_STP__USBOTG_STP, 109 /*Keyboard*/ 110 MX31_PIN_KEY_ROW0_KEY_ROW0, 111 MX31_PIN_KEY_ROW1_KEY_ROW1, 112 MX31_PIN_KEY_ROW2_KEY_ROW2, 113 MX31_PIN_KEY_COL0_KEY_COL0, 114 MX31_PIN_KEY_COL1_KEY_COL1, 115 MX31_PIN_KEY_COL2_KEY_COL2, 116 MX31_PIN_KEY_COL3_KEY_COL3, 117}; 118 119/* 120 * Matrix keyboard 121 */ 122 123static const uint32_t mx31_3ds_keymap[] = { 124 KEY(0, 0, KEY_UP), 125 KEY(0, 1, KEY_DOWN), 126 KEY(1, 0, KEY_RIGHT), 127 KEY(1, 1, KEY_LEFT), 128 KEY(1, 2, KEY_ENTER), 129 KEY(2, 0, KEY_F6), 130 KEY(2, 1, KEY_F8), 131 KEY(2, 2, KEY_F9), 132 KEY(2, 3, KEY_F10), 133}; 134 135static struct matrix_keymap_data mx31_3ds_keymap_data = { 136 .keymap = mx31_3ds_keymap, 137 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), 138}; 139 140/* Regulators */ 141static struct regulator_init_data pwgtx_init = { 142 .constraints = { 143 .boot_on = 1, 144 .always_on = 1, 145 }, 146}; 147 148static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { 149 { 150 .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */ 151 .init_data = &pwgtx_init, 152 }, { 153 .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */ 154 .init_data = &pwgtx_init, 155 }, 156}; 157 158/* MC13783 */ 159static struct mc13783_platform_data mc13783_pdata __initdata = { 160 .regulators = mx31_3ds_regulators, 161 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), 162 .flags = MC13783_USE_REGULATOR, 163}; 164 165/* SPI */ 166static int spi1_internal_chipselect[] = { 167 MXC_SPI_CS(0), 168 MXC_SPI_CS(2), 169}; 170 171static const struct spi_imx_master spi1_pdata __initconst = { 172 .chipselect = spi1_internal_chipselect, 173 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect), 174}; 175 176static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { 177 { 178 .modalias = "mc13783", 179 .max_speed_hz = 1000000, 180 .bus_num = 1, 181 .chip_select = 1, /* SS2 */ 182 .platform_data = &mc13783_pdata, 183 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), 184 .mode = SPI_CS_HIGH, 185 }, 186}; 187 188/* 189 * NAND Flash 190 */ 191static const struct mxc_nand_platform_data 192mx31_3ds_nand_board_info __initconst = { 193 .width = 1, 194 .hw_ecc = 1, 195#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT 196 .flash_bbt = 1, 197#endif 198}; 199 200/* 201 * USB OTG 202 */ 203 204#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ 205 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) 206 207#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) 208 209static int mx31_3ds_usbotg_init(void) 210{ 211 int err; 212 213 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); 214 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); 215 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); 216 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); 217 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); 218 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); 219 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); 220 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); 221 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); 222 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); 223 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); 224 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); 225 226 err = gpio_request(USBOTG_RST_B, "otgusb-reset"); 227 if (err) { 228 pr_err("Failed to request the USB OTG reset gpio\n"); 229 return err; 230 } 231 232 err = gpio_direction_output(USBOTG_RST_B, 0); 233 if (err) { 234 pr_err("Failed to drive the USB OTG reset gpio\n"); 235 goto usbotg_free_reset; 236 } 237 238 mdelay(1); 239 gpio_set_value(USBOTG_RST_B, 1); 240 return 0; 241 242usbotg_free_reset: 243 gpio_free(USBOTG_RST_B); 244 return err; 245} 246 247static struct fsl_usb2_platform_data usbotg_pdata = { 248 .operating_mode = FSL_USB2_DR_DEVICE, 249 .phy_mode = FSL_USB2_PHY_ULPI, 250}; 251 252static const struct imxuart_platform_data uart_pdata __initconst = { 253 .flags = IMXUART_HAVE_RTSCTS, 254}; 255 256/* 257 * Set up static virtual mappings. 258 */ 259static void __init mx31_3ds_map_io(void) 260{ 261 mx31_map_io(); 262} 263 264/*! 265 * Board specific initialization. 266 */ 267static void __init mxc_board_init(void) 268{ 269 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), 270 "mx31_3ds"); 271 272 imx31_add_imx_uart0(&uart_pdata); 273 imx31_add_mxc_nand(&mx31_3ds_nand_board_info); 274 275 imx31_add_spi_imx0(&spi1_pdata); 276 spi_register_board_info(mx31_3ds_spi_devs, 277 ARRAY_SIZE(mx31_3ds_spi_devs)); 278 279 mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data); 280 281 mx31_3ds_usbotg_init(); 282 mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata); 283 284 if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT)) 285 printk(KERN_WARNING "Init of the debugboard failed, all " 286 "devices on the board are unusable.\n"); 287} 288 289static void __init mx31_3ds_timer_init(void) 290{ 291 mx31_clocks_init(26000000); 292} 293 294static struct sys_timer mx31_3ds_timer = { 295 .init = mx31_3ds_timer_init, 296}; 297 298/* 299 * The following uses standard kernel macros defined in arch.h in order to 300 * initialize __mach_desc_MX31_3DS data structure. 301 */ 302MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") 303 /* Maintainer: Freescale Semiconductor, Inc. */ 304 .phys_io = MX31_AIPS1_BASE_ADDR, 305 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, 306 .boot_params = MX3x_PHYS_OFFSET + 0x100, 307 .map_io = mx31_3ds_map_io, 308 .init_irq = mx31_init_irq, 309 .init_machine = mxc_board_init, 310 .timer = &mx31_3ds_timer, 311MACHINE_END 312