1/* 2 * linux/arch/arm/mach-mmp/pxa168.c 3 * 4 * Code specific to PXA168 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#include <linux/module.h> 12#include <linux/kernel.h> 13#include <linux/init.h> 14#include <linux/list.h> 15#include <linux/io.h> 16#include <linux/clk.h> 17 18#include <asm/mach/time.h> 19#include <mach/addr-map.h> 20#include <mach/cputype.h> 21#include <mach/regs-apbc.h> 22#include <mach/regs-apmu.h> 23#include <mach/irqs.h> 24#include <mach/gpio.h> 25#include <mach/dma.h> 26#include <mach/devices.h> 27#include <mach/mfp.h> 28 29#include "common.h" 30#include "clock.h" 31 32#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) 33 34static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata = 35{ 36 MFP_ADDR_X(GPIO0, GPIO36, 0x04c), 37 MFP_ADDR_X(GPIO37, GPIO55, 0x000), 38 MFP_ADDR_X(GPIO56, GPIO123, 0x0e0), 39 MFP_ADDR_X(GPIO124, GPIO127, 0x0f4), 40 41 MFP_ADDR_END, 42}; 43 44#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) 45 46static void __init pxa168_init_gpio(void) 47{ 48 int i; 49 50 /* enable GPIO clock */ 51 __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO); 52 53 /* unmask GPIO edge detection for all 4 banks - APMASKx */ 54 for (i = 0; i < 4; i++) 55 __raw_writel(0xffffffff, APMASK(i)); 56 57 pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL); 58} 59 60void __init pxa168_init_irq(void) 61{ 62 icu_init_irq(); 63 pxa168_init_gpio(); 64} 65 66/* APB peripheral clocks */ 67static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); 68static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); 69static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); 70static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); 71static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000); 72static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000); 73static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); 74static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); 75static APBC_CLK(ssp1, PXA168_SSP1, 4, 0); 76static APBC_CLK(ssp2, PXA168_SSP2, 4, 0); 77static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); 78static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); 79static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); 80 81static APMU_CLK(nand, NAND, 0x01db, 208000000); 82 83/* device and clock bindings */ 84static struct clk_lookup pxa168_clkregs[] = { 85 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), 86 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), 87 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), 88 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), 89 INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), 90 INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), 91 INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), 92 INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), 93 INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), 94 INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), 95 INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), 96 INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), 97 INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), 98 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), 99}; 100 101static int __init pxa168_init(void) 102{ 103 if (cpu_is_pxa168()) { 104 mfp_init_base(MFPR_VIRT_BASE); 105 mfp_init_addr(pxa168_mfp_addr_map); 106 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); 107 clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); 108 } 109 110 return 0; 111} 112postcore_initcall(pxa168_init); 113 114/* system timer - clock enabled, 3.25MHz */ 115#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) 116 117static void __init pxa168_timer_init(void) 118{ 119 /* this is early, we have to initialize the CCU registers by 120 * ourselves instead of using clk_* API. Clock rate is defined 121 * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running 122 */ 123 __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); 124 125 /* 3.25MHz, bus/functional clock enabled, release reset */ 126 __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); 127 128 timer_init(IRQ_PXA168_TIMER1); 129} 130 131struct sys_timer pxa168_timer = { 132 .init = pxa168_timer_init, 133}; 134 135/* on-chip devices */ 136PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); 137PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); 138PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28); 139PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28); 140PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10); 141PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10); 142PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10); 143PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10); 144PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); 145PXA168_DEVICE(ssp1, "pxa168-ssp", 0, SSP1, 0xd401b000, 0x40, 52, 53); 146PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55); 147PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57); 148PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59); 149PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61); 150