1/* 2 * linux/arch/arm/mach-integrator/integrator_ap.c 3 * 4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20#include <linux/types.h> 21#include <linux/kernel.h> 22#include <linux/init.h> 23#include <linux/list.h> 24#include <linux/platform_device.h> 25#include <linux/slab.h> 26#include <linux/string.h> 27#include <linux/sysdev.h> 28#include <linux/amba/bus.h> 29#include <linux/amba/kmi.h> 30#include <linux/clocksource.h> 31#include <linux/clockchips.h> 32#include <linux/interrupt.h> 33#include <linux/io.h> 34 35#include <mach/hardware.h> 36#include <mach/platform.h> 37#include <asm/hardware/arm_timer.h> 38#include <asm/irq.h> 39#include <asm/setup.h> 40#include <asm/param.h> /* HZ */ 41#include <asm/mach-types.h> 42 43#include <mach/lm.h> 44 45#include <asm/mach/arch.h> 46#include <asm/mach/flash.h> 47#include <asm/mach/irq.h> 48#include <asm/mach/map.h> 49#include <asm/mach/time.h> 50 51#include "common.h" 52 53#define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) 54#define VA_SC_BASE IO_ADDRESS(INTEGRATOR_SC_BASE) 55#define VA_EBI_BASE IO_ADDRESS(INTEGRATOR_EBI_BASE) 56#define VA_CMIC_BASE IO_ADDRESS(INTEGRATOR_HDR_IC) 57 58/* 59 * Logical Physical 60 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) 61 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) 62 * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) 63 * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) 64 * ef000000 Cache flush 65 * f1000000 10000000 Core module registers 66 * f1100000 11000000 System controller registers 67 * f1200000 12000000 EBI registers 68 * f1300000 13000000 Counter/Timer 69 * f1400000 14000000 Interrupt controller 70 * f1600000 16000000 UART 0 71 * f1700000 17000000 UART 1 72 * f1a00000 1a000000 Debug LEDs 73 * f1b00000 1b000000 GPIO 74 */ 75 76static struct map_desc ap_io_desc[] __initdata = { 77 { 78 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), 79 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), 80 .length = SZ_4K, 81 .type = MT_DEVICE 82 }, { 83 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE), 84 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE), 85 .length = SZ_4K, 86 .type = MT_DEVICE 87 }, { 88 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), 89 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), 90 .length = SZ_4K, 91 .type = MT_DEVICE 92 }, { 93 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), 94 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), 95 .length = SZ_4K, 96 .type = MT_DEVICE 97 }, { 98 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), 99 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), 100 .length = SZ_4K, 101 .type = MT_DEVICE 102 }, { 103 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), 104 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), 105 .length = SZ_4K, 106 .type = MT_DEVICE 107 }, { 108 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE), 109 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE), 110 .length = SZ_4K, 111 .type = MT_DEVICE 112 }, { 113 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), 114 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), 115 .length = SZ_4K, 116 .type = MT_DEVICE 117 }, { 118 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE), 119 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE), 120 .length = SZ_4K, 121 .type = MT_DEVICE 122 }, { 123 .virtual = PCI_MEMORY_VADDR, 124 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), 125 .length = SZ_16M, 126 .type = MT_DEVICE 127 }, { 128 .virtual = PCI_CONFIG_VADDR, 129 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), 130 .length = SZ_16M, 131 .type = MT_DEVICE 132 }, { 133 .virtual = PCI_V3_VADDR, 134 .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), 135 .length = SZ_64K, 136 .type = MT_DEVICE 137 }, { 138 .virtual = PCI_IO_VADDR, 139 .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE), 140 .length = SZ_64K, 141 .type = MT_DEVICE 142 } 143}; 144 145static void __init ap_map_io(void) 146{ 147 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); 148} 149 150#define INTEGRATOR_SC_VALID_INT 0x003fffff 151 152static void sc_mask_irq(unsigned int irq) 153{ 154 writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_CLEAR); 155} 156 157static void sc_unmask_irq(unsigned int irq) 158{ 159 writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_SET); 160} 161 162static struct irq_chip sc_chip = { 163 .name = "SC", 164 .ack = sc_mask_irq, 165 .mask = sc_mask_irq, 166 .unmask = sc_unmask_irq, 167}; 168 169static void __init ap_init_irq(void) 170{ 171 unsigned int i; 172 173 /* Disable all interrupts initially. */ 174 /* Do the core module ones */ 175 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); 176 177 /* do the header card stuff next */ 178 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); 179 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); 180 181 for (i = 0; i < NR_IRQS; i++) { 182 if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) { 183 set_irq_chip(i, &sc_chip); 184 set_irq_handler(i, handle_level_irq); 185 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 186 } 187 } 188} 189 190#ifdef CONFIG_PM 191static unsigned long ic_irq_enable; 192 193static int irq_suspend(struct sys_device *dev, pm_message_t state) 194{ 195 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); 196 return 0; 197} 198 199static int irq_resume(struct sys_device *dev) 200{ 201 /* disable all irq sources */ 202 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); 203 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); 204 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); 205 206 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); 207 return 0; 208} 209#else 210#define irq_suspend NULL 211#define irq_resume NULL 212#endif 213 214static struct sysdev_class irq_class = { 215 .name = "irq", 216 .suspend = irq_suspend, 217 .resume = irq_resume, 218}; 219 220static struct sys_device irq_device = { 221 .id = 0, 222 .cls = &irq_class, 223}; 224 225static int __init irq_init_sysfs(void) 226{ 227 int ret = sysdev_class_register(&irq_class); 228 if (ret == 0) 229 ret = sysdev_register(&irq_device); 230 return ret; 231} 232 233device_initcall(irq_init_sysfs); 234 235/* 236 * Flash handling. 237 */ 238#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) 239#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) 240#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) 241#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) 242 243static int ap_flash_init(void) 244{ 245 u32 tmp; 246 247 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC); 248 249 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE; 250 writel(tmp, EBI_CSR1); 251 252 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) { 253 writel(0xa05f, EBI_LOCK); 254 writel(tmp, EBI_CSR1); 255 writel(0, EBI_LOCK); 256 } 257 return 0; 258} 259 260static void ap_flash_exit(void) 261{ 262 u32 tmp; 263 264 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC); 265 266 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE; 267 writel(tmp, EBI_CSR1); 268 269 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) { 270 writel(0xa05f, EBI_LOCK); 271 writel(tmp, EBI_CSR1); 272 writel(0, EBI_LOCK); 273 } 274} 275 276static void ap_flash_set_vpp(int on) 277{ 278 unsigned long reg = on ? SC_CTRLS : SC_CTRLC; 279 280 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg); 281} 282 283static struct flash_platform_data ap_flash_data = { 284 .map_name = "cfi_probe", 285 .width = 4, 286 .init = ap_flash_init, 287 .exit = ap_flash_exit, 288 .set_vpp = ap_flash_set_vpp, 289}; 290 291static struct resource cfi_flash_resource = { 292 .start = INTEGRATOR_FLASH_BASE, 293 .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, 294 .flags = IORESOURCE_MEM, 295}; 296 297static struct platform_device cfi_flash_device = { 298 .name = "armflash", 299 .id = 0, 300 .dev = { 301 .platform_data = &ap_flash_data, 302 }, 303 .num_resources = 1, 304 .resource = &cfi_flash_resource, 305}; 306 307static void __init ap_init(void) 308{ 309 unsigned long sc_dec; 310 int i; 311 312 platform_device_register(&cfi_flash_device); 313 314 sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET); 315 for (i = 0; i < 4; i++) { 316 struct lm_device *lmdev; 317 318 if ((sc_dec & (16 << i)) == 0) 319 continue; 320 321 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); 322 if (!lmdev) 323 continue; 324 325 lmdev->resource.start = 0xc0000000 + 0x10000000 * i; 326 lmdev->resource.end = lmdev->resource.start + 0x0fffffff; 327 lmdev->resource.flags = IORESOURCE_MEM; 328 lmdev->irq = IRQ_AP_EXPINT0 + i; 329 lmdev->id = i; 330 331 lm_device_register(lmdev); 332 } 333} 334 335/* 336 * Where is the timer (VA)? 337 */ 338#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE) 339#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE) 340#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE) 341 342/* 343 * How long is the timer interval? 344 */ 345#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) 346#if TIMER_INTERVAL >= 0x100000 347#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) 348#elif TIMER_INTERVAL >= 0x10000 349#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) 350#else 351#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) 352#endif 353 354static unsigned long timer_reload; 355 356static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE; 357 358static cycle_t timersp_read(struct clocksource *cs) 359{ 360 return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff); 361} 362 363static struct clocksource clocksource_timersp = { 364 .name = "timer2", 365 .rating = 200, 366 .read = timersp_read, 367 .mask = CLOCKSOURCE_MASK(16), 368 .shift = 16, 369 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 370}; 371 372static void integrator_clocksource_init(u32 khz) 373{ 374 struct clocksource *cs = &clocksource_timersp; 375 void __iomem *base = clksrc_base; 376 u32 ctrl = TIMER_CTRL_ENABLE; 377 378 if (khz >= 1500) { 379 khz /= 16; 380 ctrl = TIMER_CTRL_DIV16; 381 } 382 383 writel(ctrl, base + TIMER_CTRL); 384 writel(0xffff, base + TIMER_LOAD); 385 386 cs->mult = clocksource_khz2mult(khz, cs->shift); 387 clocksource_register(cs); 388} 389 390static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE; 391 392/* 393 * IRQ handler for the timer 394 */ 395static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id) 396{ 397 struct clock_event_device *evt = dev_id; 398 399 /* clear the interrupt */ 400 writel(1, clkevt_base + TIMER_INTCLR); 401 402 evt->event_handler(evt); 403 404 return IRQ_HANDLED; 405} 406 407static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) 408{ 409 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE; 410 411 BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT); 412 413 if (mode == CLOCK_EVT_MODE_PERIODIC) { 414 writel(ctrl, clkevt_base + TIMER_CTRL); 415 writel(timer_reload, clkevt_base + TIMER_LOAD); 416 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; 417 } 418 419 writel(ctrl, clkevt_base + TIMER_CTRL); 420} 421 422static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt) 423{ 424 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); 425 426 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); 427 writel(next, clkevt_base + TIMER_LOAD); 428 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); 429 430 return 0; 431} 432 433static struct clock_event_device integrator_clockevent = { 434 .name = "timer1", 435 .shift = 34, 436 .features = CLOCK_EVT_FEAT_PERIODIC, 437 .set_mode = clkevt_set_mode, 438 .set_next_event = clkevt_set_next_event, 439 .rating = 300, 440 .cpumask = cpu_all_mask, 441}; 442 443static struct irqaction integrator_timer_irq = { 444 .name = "timer", 445 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 446 .handler = integrator_timer_interrupt, 447 .dev_id = &integrator_clockevent, 448}; 449 450static void integrator_clockevent_init(u32 khz) 451{ 452 struct clock_event_device *evt = &integrator_clockevent; 453 unsigned int ctrl = 0; 454 455 if (khz * 1000 > 0x100000 * HZ) { 456 khz /= 256; 457 ctrl |= TIMER_CTRL_DIV256; 458 } else if (khz * 1000 > 0x10000 * HZ) { 459 khz /= 16; 460 ctrl |= TIMER_CTRL_DIV16; 461 } 462 463 timer_reload = khz * 1000 / HZ; 464 writel(ctrl, clkevt_base + TIMER_CTRL); 465 466 evt->irq = IRQ_TIMERINT1; 467 evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift); 468 evt->max_delta_ns = clockevent_delta2ns(0xffff, evt); 469 evt->min_delta_ns = clockevent_delta2ns(0xf, evt); 470 471 setup_irq(IRQ_TIMERINT1, &integrator_timer_irq); 472 clockevents_register_device(evt); 473} 474 475/* 476 * Set up timer(s). 477 */ 478static void __init ap_init_timer(void) 479{ 480 u32 khz = TICKS_PER_uSEC * 1000; 481 482 writel(0, TIMER0_VA_BASE + TIMER_CTRL); 483 writel(0, TIMER1_VA_BASE + TIMER_CTRL); 484 writel(0, TIMER2_VA_BASE + TIMER_CTRL); 485 486 integrator_clocksource_init(khz); 487 integrator_clockevent_init(khz); 488} 489 490static struct sys_timer ap_timer = { 491 .init = ap_init_timer, 492}; 493 494MACHINE_START(INTEGRATOR, "ARM-Integrator") 495 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 496 .phys_io = 0x16000000, 497 .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc, 498 .boot_params = 0x00000100, 499 .map_io = ap_map_io, 500 .reserve = integrator_reserve, 501 .init_irq = ap_init_irq, 502 .timer = &ap_timer, 503 .init_machine = ap_init, 504MACHINE_END 505