1/* 2 * arch/arm/mach-dove/common.c 3 * 4 * Core functions for Marvell Dove 88AP510 System On Chip 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11#include <linux/kernel.h> 12#include <linux/delay.h> 13#include <linux/init.h> 14#include <linux/platform_device.h> 15#include <linux/pci.h> 16#include <linux/serial_8250.h> 17#include <linux/clk.h> 18#include <linux/mbus.h> 19#include <linux/mv643xx_eth.h> 20#include <linux/mv643xx_i2c.h> 21#include <linux/ata_platform.h> 22#include <linux/spi/orion_spi.h> 23#include <linux/gpio.h> 24#include <asm/page.h> 25#include <asm/setup.h> 26#include <asm/timex.h> 27#include <asm/hardware/cache-tauros2.h> 28#include <asm/mach/map.h> 29#include <asm/mach/time.h> 30#include <asm/mach/pci.h> 31#include <mach/dove.h> 32#include <mach/bridge-regs.h> 33#include <asm/mach/arch.h> 34#include <linux/irq.h> 35#include <plat/mv_xor.h> 36#include <plat/ehci-orion.h> 37#include <plat/time.h> 38#include "common.h" 39 40/***************************************************************************** 41 * I/O Address Mapping 42 ****************************************************************************/ 43static struct map_desc dove_io_desc[] __initdata = { 44 { 45 .virtual = DOVE_SB_REGS_VIRT_BASE, 46 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), 47 .length = DOVE_SB_REGS_SIZE, 48 .type = MT_DEVICE, 49 }, { 50 .virtual = DOVE_NB_REGS_VIRT_BASE, 51 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), 52 .length = DOVE_NB_REGS_SIZE, 53 .type = MT_DEVICE, 54 }, { 55 .virtual = DOVE_PCIE0_IO_VIRT_BASE, 56 .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), 57 .length = DOVE_PCIE0_IO_SIZE, 58 .type = MT_DEVICE, 59 }, { 60 .virtual = DOVE_PCIE1_IO_VIRT_BASE, 61 .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), 62 .length = DOVE_PCIE1_IO_SIZE, 63 .type = MT_DEVICE, 64 }, 65}; 66 67void __init dove_map_io(void) 68{ 69 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); 70} 71 72/***************************************************************************** 73 * EHCI 74 ****************************************************************************/ 75static struct orion_ehci_data dove_ehci_data = { 76 .dram = &dove_mbus_dram_info, 77 .phy_version = EHCI_PHY_NA, 78}; 79 80static u64 ehci_dmamask = DMA_BIT_MASK(32); 81 82/***************************************************************************** 83 * EHCI0 84 ****************************************************************************/ 85static struct resource dove_ehci0_resources[] = { 86 { 87 .start = DOVE_USB0_PHYS_BASE, 88 .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1, 89 .flags = IORESOURCE_MEM, 90 }, { 91 .start = IRQ_DOVE_USB0, 92 .end = IRQ_DOVE_USB0, 93 .flags = IORESOURCE_IRQ, 94 }, 95}; 96 97static struct platform_device dove_ehci0 = { 98 .name = "orion-ehci", 99 .id = 0, 100 .dev = { 101 .dma_mask = &ehci_dmamask, 102 .coherent_dma_mask = DMA_BIT_MASK(32), 103 .platform_data = &dove_ehci_data, 104 }, 105 .resource = dove_ehci0_resources, 106 .num_resources = ARRAY_SIZE(dove_ehci0_resources), 107}; 108 109void __init dove_ehci0_init(void) 110{ 111 platform_device_register(&dove_ehci0); 112} 113 114/***************************************************************************** 115 * EHCI1 116 ****************************************************************************/ 117static struct resource dove_ehci1_resources[] = { 118 { 119 .start = DOVE_USB1_PHYS_BASE, 120 .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1, 121 .flags = IORESOURCE_MEM, 122 }, { 123 .start = IRQ_DOVE_USB1, 124 .end = IRQ_DOVE_USB1, 125 .flags = IORESOURCE_IRQ, 126 }, 127}; 128 129static struct platform_device dove_ehci1 = { 130 .name = "orion-ehci", 131 .id = 1, 132 .dev = { 133 .dma_mask = &ehci_dmamask, 134 .coherent_dma_mask = DMA_BIT_MASK(32), 135 .platform_data = &dove_ehci_data, 136 }, 137 .resource = dove_ehci1_resources, 138 .num_resources = ARRAY_SIZE(dove_ehci1_resources), 139}; 140 141void __init dove_ehci1_init(void) 142{ 143 platform_device_register(&dove_ehci1); 144} 145 146/***************************************************************************** 147 * GE00 148 ****************************************************************************/ 149struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = { 150 .t_clk = 0, 151 .dram = &dove_mbus_dram_info, 152}; 153 154static struct resource dove_ge00_shared_resources[] = { 155 { 156 .name = "ge00 base", 157 .start = DOVE_GE00_PHYS_BASE + 0x2000, 158 .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1, 159 .flags = IORESOURCE_MEM, 160 }, 161}; 162 163static struct platform_device dove_ge00_shared = { 164 .name = MV643XX_ETH_SHARED_NAME, 165 .id = 0, 166 .dev = { 167 .platform_data = &dove_ge00_shared_data, 168 }, 169 .num_resources = 1, 170 .resource = dove_ge00_shared_resources, 171}; 172 173static struct resource dove_ge00_resources[] = { 174 { 175 .name = "ge00 irq", 176 .start = IRQ_DOVE_GE00_SUM, 177 .end = IRQ_DOVE_GE00_SUM, 178 .flags = IORESOURCE_IRQ, 179 }, 180}; 181 182static struct platform_device dove_ge00 = { 183 .name = MV643XX_ETH_NAME, 184 .id = 0, 185 .num_resources = 1, 186 .resource = dove_ge00_resources, 187 .dev = { 188 .coherent_dma_mask = 0xffffffff, 189 }, 190}; 191 192void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 193{ 194 eth_data->shared = &dove_ge00_shared; 195 dove_ge00.dev.platform_data = eth_data; 196 197 platform_device_register(&dove_ge00_shared); 198 platform_device_register(&dove_ge00); 199} 200 201/***************************************************************************** 202 * SoC RTC 203 ****************************************************************************/ 204static struct resource dove_rtc_resource[] = { 205 { 206 .start = DOVE_RTC_PHYS_BASE, 207 .end = DOVE_RTC_PHYS_BASE + 32 - 1, 208 .flags = IORESOURCE_MEM, 209 }, { 210 .start = IRQ_DOVE_RTC, 211 .flags = IORESOURCE_IRQ, 212 } 213}; 214 215void __init dove_rtc_init(void) 216{ 217 platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2); 218} 219 220/***************************************************************************** 221 * SATA 222 ****************************************************************************/ 223static struct resource dove_sata_resources[] = { 224 { 225 .name = "sata base", 226 .start = DOVE_SATA_PHYS_BASE, 227 .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1, 228 .flags = IORESOURCE_MEM, 229 }, { 230 .name = "sata irq", 231 .start = IRQ_DOVE_SATA, 232 .end = IRQ_DOVE_SATA, 233 .flags = IORESOURCE_IRQ, 234 }, 235}; 236 237static struct platform_device dove_sata = { 238 .name = "sata_mv", 239 .id = 0, 240 .dev = { 241 .coherent_dma_mask = DMA_BIT_MASK(32), 242 }, 243 .num_resources = ARRAY_SIZE(dove_sata_resources), 244 .resource = dove_sata_resources, 245}; 246 247void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 248{ 249 sata_data->dram = &dove_mbus_dram_info; 250 dove_sata.dev.platform_data = sata_data; 251 platform_device_register(&dove_sata); 252} 253 254/***************************************************************************** 255 * UART0 256 ****************************************************************************/ 257static struct plat_serial8250_port dove_uart0_data[] = { 258 { 259 .mapbase = DOVE_UART0_PHYS_BASE, 260 .membase = (char *)DOVE_UART0_VIRT_BASE, 261 .irq = IRQ_DOVE_UART_0, 262 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 263 .iotype = UPIO_MEM, 264 .regshift = 2, 265 .uartclk = 0, 266 }, { 267 }, 268}; 269 270static struct resource dove_uart0_resources[] = { 271 { 272 .start = DOVE_UART0_PHYS_BASE, 273 .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1, 274 .flags = IORESOURCE_MEM, 275 }, { 276 .start = IRQ_DOVE_UART_0, 277 .end = IRQ_DOVE_UART_0, 278 .flags = IORESOURCE_IRQ, 279 }, 280}; 281 282static struct platform_device dove_uart0 = { 283 .name = "serial8250", 284 .id = 0, 285 .dev = { 286 .platform_data = dove_uart0_data, 287 }, 288 .resource = dove_uart0_resources, 289 .num_resources = ARRAY_SIZE(dove_uart0_resources), 290}; 291 292void __init dove_uart0_init(void) 293{ 294 platform_device_register(&dove_uart0); 295} 296 297/***************************************************************************** 298 * UART1 299 ****************************************************************************/ 300static struct plat_serial8250_port dove_uart1_data[] = { 301 { 302 .mapbase = DOVE_UART1_PHYS_BASE, 303 .membase = (char *)DOVE_UART1_VIRT_BASE, 304 .irq = IRQ_DOVE_UART_1, 305 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 306 .iotype = UPIO_MEM, 307 .regshift = 2, 308 .uartclk = 0, 309 }, { 310 }, 311}; 312 313static struct resource dove_uart1_resources[] = { 314 { 315 .start = DOVE_UART1_PHYS_BASE, 316 .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1, 317 .flags = IORESOURCE_MEM, 318 }, { 319 .start = IRQ_DOVE_UART_1, 320 .end = IRQ_DOVE_UART_1, 321 .flags = IORESOURCE_IRQ, 322 }, 323}; 324 325static struct platform_device dove_uart1 = { 326 .name = "serial8250", 327 .id = 1, 328 .dev = { 329 .platform_data = dove_uart1_data, 330 }, 331 .resource = dove_uart1_resources, 332 .num_resources = ARRAY_SIZE(dove_uart1_resources), 333}; 334 335void __init dove_uart1_init(void) 336{ 337 platform_device_register(&dove_uart1); 338} 339 340/***************************************************************************** 341 * UART2 342 ****************************************************************************/ 343static struct plat_serial8250_port dove_uart2_data[] = { 344 { 345 .mapbase = DOVE_UART2_PHYS_BASE, 346 .membase = (char *)DOVE_UART2_VIRT_BASE, 347 .irq = IRQ_DOVE_UART_2, 348 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 349 .iotype = UPIO_MEM, 350 .regshift = 2, 351 .uartclk = 0, 352 }, { 353 }, 354}; 355 356static struct resource dove_uart2_resources[] = { 357 { 358 .start = DOVE_UART2_PHYS_BASE, 359 .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1, 360 .flags = IORESOURCE_MEM, 361 }, { 362 .start = IRQ_DOVE_UART_2, 363 .end = IRQ_DOVE_UART_2, 364 .flags = IORESOURCE_IRQ, 365 }, 366}; 367 368static struct platform_device dove_uart2 = { 369 .name = "serial8250", 370 .id = 2, 371 .dev = { 372 .platform_data = dove_uart2_data, 373 }, 374 .resource = dove_uart2_resources, 375 .num_resources = ARRAY_SIZE(dove_uart2_resources), 376}; 377 378void __init dove_uart2_init(void) 379{ 380 platform_device_register(&dove_uart2); 381} 382 383/***************************************************************************** 384 * UART3 385 ****************************************************************************/ 386static struct plat_serial8250_port dove_uart3_data[] = { 387 { 388 .mapbase = DOVE_UART3_PHYS_BASE, 389 .membase = (char *)DOVE_UART3_VIRT_BASE, 390 .irq = IRQ_DOVE_UART_3, 391 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 392 .iotype = UPIO_MEM, 393 .regshift = 2, 394 .uartclk = 0, 395 }, { 396 }, 397}; 398 399static struct resource dove_uart3_resources[] = { 400 { 401 .start = DOVE_UART3_PHYS_BASE, 402 .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1, 403 .flags = IORESOURCE_MEM, 404 }, { 405 .start = IRQ_DOVE_UART_3, 406 .end = IRQ_DOVE_UART_3, 407 .flags = IORESOURCE_IRQ, 408 }, 409}; 410 411static struct platform_device dove_uart3 = { 412 .name = "serial8250", 413 .id = 3, 414 .dev = { 415 .platform_data = dove_uart3_data, 416 }, 417 .resource = dove_uart3_resources, 418 .num_resources = ARRAY_SIZE(dove_uart3_resources), 419}; 420 421void __init dove_uart3_init(void) 422{ 423 platform_device_register(&dove_uart3); 424} 425 426/***************************************************************************** 427 * SPI0 428 ****************************************************************************/ 429static struct orion_spi_info dove_spi0_data = { 430 .tclk = 0, 431}; 432 433static struct resource dove_spi0_resources[] = { 434 { 435 .start = DOVE_SPI0_PHYS_BASE, 436 .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1, 437 .flags = IORESOURCE_MEM, 438 }, { 439 .start = IRQ_DOVE_SPI0, 440 .end = IRQ_DOVE_SPI0, 441 .flags = IORESOURCE_IRQ, 442 }, 443}; 444 445static struct platform_device dove_spi0 = { 446 .name = "orion_spi", 447 .id = 0, 448 .resource = dove_spi0_resources, 449 .dev = { 450 .platform_data = &dove_spi0_data, 451 }, 452 .num_resources = ARRAY_SIZE(dove_spi0_resources), 453}; 454 455void __init dove_spi0_init(void) 456{ 457 platform_device_register(&dove_spi0); 458} 459 460/***************************************************************************** 461 * SPI1 462 ****************************************************************************/ 463static struct orion_spi_info dove_spi1_data = { 464 .tclk = 0, 465}; 466 467static struct resource dove_spi1_resources[] = { 468 { 469 .start = DOVE_SPI1_PHYS_BASE, 470 .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1, 471 .flags = IORESOURCE_MEM, 472 }, { 473 .start = IRQ_DOVE_SPI1, 474 .end = IRQ_DOVE_SPI1, 475 .flags = IORESOURCE_IRQ, 476 }, 477}; 478 479static struct platform_device dove_spi1 = { 480 .name = "orion_spi", 481 .id = 1, 482 .resource = dove_spi1_resources, 483 .dev = { 484 .platform_data = &dove_spi1_data, 485 }, 486 .num_resources = ARRAY_SIZE(dove_spi1_resources), 487}; 488 489void __init dove_spi1_init(void) 490{ 491 platform_device_register(&dove_spi1); 492} 493 494/***************************************************************************** 495 * I2C 496 ****************************************************************************/ 497static struct mv64xxx_i2c_pdata dove_i2c_data = { 498 .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */ 499 .freq_n = 3, 500 .timeout = 1000, /* Default timeout of 1 second */ 501}; 502 503static struct resource dove_i2c_resources[] = { 504 { 505 .name = "i2c base", 506 .start = DOVE_I2C_PHYS_BASE, 507 .end = DOVE_I2C_PHYS_BASE + 0x20 - 1, 508 .flags = IORESOURCE_MEM, 509 }, { 510 .name = "i2c irq", 511 .start = IRQ_DOVE_I2C, 512 .end = IRQ_DOVE_I2C, 513 .flags = IORESOURCE_IRQ, 514 }, 515}; 516 517static struct platform_device dove_i2c = { 518 .name = MV64XXX_I2C_CTLR_NAME, 519 .id = 0, 520 .num_resources = ARRAY_SIZE(dove_i2c_resources), 521 .resource = dove_i2c_resources, 522 .dev = { 523 .platform_data = &dove_i2c_data, 524 }, 525}; 526 527void __init dove_i2c_init(void) 528{ 529 platform_device_register(&dove_i2c); 530} 531 532/***************************************************************************** 533 * Time handling 534 ****************************************************************************/ 535static int get_tclk(void) 536{ 537 /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */ 538 return 166666667; 539} 540 541static void dove_timer_init(void) 542{ 543 orion_time_init(IRQ_DOVE_BRIDGE, get_tclk()); 544} 545 546struct sys_timer dove_timer = { 547 .init = dove_timer_init, 548}; 549 550/***************************************************************************** 551 * XOR 552 ****************************************************************************/ 553static struct mv_xor_platform_shared_data dove_xor_shared_data = { 554 .dram = &dove_mbus_dram_info, 555}; 556 557/***************************************************************************** 558 * XOR 0 559 ****************************************************************************/ 560static u64 dove_xor0_dmamask = DMA_BIT_MASK(32); 561 562static struct resource dove_xor0_shared_resources[] = { 563 { 564 .name = "xor 0 low", 565 .start = DOVE_XOR0_PHYS_BASE, 566 .end = DOVE_XOR0_PHYS_BASE + 0xff, 567 .flags = IORESOURCE_MEM, 568 }, { 569 .name = "xor 0 high", 570 .start = DOVE_XOR0_HIGH_PHYS_BASE, 571 .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff, 572 .flags = IORESOURCE_MEM, 573 }, 574}; 575 576static struct platform_device dove_xor0_shared = { 577 .name = MV_XOR_SHARED_NAME, 578 .id = 0, 579 .dev = { 580 .platform_data = &dove_xor_shared_data, 581 }, 582 .num_resources = ARRAY_SIZE(dove_xor0_shared_resources), 583 .resource = dove_xor0_shared_resources, 584}; 585 586static struct resource dove_xor00_resources[] = { 587 [0] = { 588 .start = IRQ_DOVE_XOR_00, 589 .end = IRQ_DOVE_XOR_00, 590 .flags = IORESOURCE_IRQ, 591 }, 592}; 593 594static struct mv_xor_platform_data dove_xor00_data = { 595 .shared = &dove_xor0_shared, 596 .hw_id = 0, 597 .pool_size = PAGE_SIZE, 598}; 599 600static struct platform_device dove_xor00_channel = { 601 .name = MV_XOR_NAME, 602 .id = 0, 603 .num_resources = ARRAY_SIZE(dove_xor00_resources), 604 .resource = dove_xor00_resources, 605 .dev = { 606 .dma_mask = &dove_xor0_dmamask, 607 .coherent_dma_mask = DMA_BIT_MASK(64), 608 .platform_data = &dove_xor00_data, 609 }, 610}; 611 612static struct resource dove_xor01_resources[] = { 613 [0] = { 614 .start = IRQ_DOVE_XOR_01, 615 .end = IRQ_DOVE_XOR_01, 616 .flags = IORESOURCE_IRQ, 617 }, 618}; 619 620static struct mv_xor_platform_data dove_xor01_data = { 621 .shared = &dove_xor0_shared, 622 .hw_id = 1, 623 .pool_size = PAGE_SIZE, 624}; 625 626static struct platform_device dove_xor01_channel = { 627 .name = MV_XOR_NAME, 628 .id = 1, 629 .num_resources = ARRAY_SIZE(dove_xor01_resources), 630 .resource = dove_xor01_resources, 631 .dev = { 632 .dma_mask = &dove_xor0_dmamask, 633 .coherent_dma_mask = DMA_BIT_MASK(64), 634 .platform_data = &dove_xor01_data, 635 }, 636}; 637 638void __init dove_xor0_init(void) 639{ 640 platform_device_register(&dove_xor0_shared); 641 642 /* 643 * two engines can't do memset simultaneously, this limitation 644 * satisfied by removing memset support from one of the engines. 645 */ 646 dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask); 647 dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask); 648 platform_device_register(&dove_xor00_channel); 649 650 dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask); 651 dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask); 652 dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask); 653 platform_device_register(&dove_xor01_channel); 654} 655 656/***************************************************************************** 657 * XOR 1 658 ****************************************************************************/ 659static u64 dove_xor1_dmamask = DMA_BIT_MASK(32); 660 661static struct resource dove_xor1_shared_resources[] = { 662 { 663 .name = "xor 0 low", 664 .start = DOVE_XOR1_PHYS_BASE, 665 .end = DOVE_XOR1_PHYS_BASE + 0xff, 666 .flags = IORESOURCE_MEM, 667 }, { 668 .name = "xor 0 high", 669 .start = DOVE_XOR1_HIGH_PHYS_BASE, 670 .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff, 671 .flags = IORESOURCE_MEM, 672 }, 673}; 674 675static struct platform_device dove_xor1_shared = { 676 .name = MV_XOR_SHARED_NAME, 677 .id = 1, 678 .dev = { 679 .platform_data = &dove_xor_shared_data, 680 }, 681 .num_resources = ARRAY_SIZE(dove_xor1_shared_resources), 682 .resource = dove_xor1_shared_resources, 683}; 684 685static struct resource dove_xor10_resources[] = { 686 [0] = { 687 .start = IRQ_DOVE_XOR_10, 688 .end = IRQ_DOVE_XOR_10, 689 .flags = IORESOURCE_IRQ, 690 }, 691}; 692 693static struct mv_xor_platform_data dove_xor10_data = { 694 .shared = &dove_xor1_shared, 695 .hw_id = 0, 696 .pool_size = PAGE_SIZE, 697}; 698 699static struct platform_device dove_xor10_channel = { 700 .name = MV_XOR_NAME, 701 .id = 2, 702 .num_resources = ARRAY_SIZE(dove_xor10_resources), 703 .resource = dove_xor10_resources, 704 .dev = { 705 .dma_mask = &dove_xor1_dmamask, 706 .coherent_dma_mask = DMA_BIT_MASK(64), 707 .platform_data = &dove_xor10_data, 708 }, 709}; 710 711static struct resource dove_xor11_resources[] = { 712 [0] = { 713 .start = IRQ_DOVE_XOR_11, 714 .end = IRQ_DOVE_XOR_11, 715 .flags = IORESOURCE_IRQ, 716 }, 717}; 718 719static struct mv_xor_platform_data dove_xor11_data = { 720 .shared = &dove_xor1_shared, 721 .hw_id = 1, 722 .pool_size = PAGE_SIZE, 723}; 724 725static struct platform_device dove_xor11_channel = { 726 .name = MV_XOR_NAME, 727 .id = 3, 728 .num_resources = ARRAY_SIZE(dove_xor11_resources), 729 .resource = dove_xor11_resources, 730 .dev = { 731 .dma_mask = &dove_xor1_dmamask, 732 .coherent_dma_mask = DMA_BIT_MASK(64), 733 .platform_data = &dove_xor11_data, 734 }, 735}; 736 737void __init dove_xor1_init(void) 738{ 739 platform_device_register(&dove_xor1_shared); 740 741 /* 742 * two engines can't do memset simultaneously, this limitation 743 * satisfied by removing memset support from one of the engines. 744 */ 745 dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask); 746 dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask); 747 platform_device_register(&dove_xor10_channel); 748 749 dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask); 750 dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask); 751 dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask); 752 platform_device_register(&dove_xor11_channel); 753} 754 755/***************************************************************************** 756 * SDIO 757 ****************************************************************************/ 758static u64 sdio_dmamask = DMA_BIT_MASK(32); 759 760static struct resource dove_sdio0_resources[] = { 761 { 762 .start = DOVE_SDIO0_PHYS_BASE, 763 .end = DOVE_SDIO0_PHYS_BASE + 0xff, 764 .flags = IORESOURCE_MEM, 765 }, { 766 .start = IRQ_DOVE_SDIO0, 767 .end = IRQ_DOVE_SDIO0, 768 .flags = IORESOURCE_IRQ, 769 }, 770}; 771 772static struct platform_device dove_sdio0 = { 773 .name = "sdhci-mv", 774 .id = 0, 775 .dev = { 776 .dma_mask = &sdio_dmamask, 777 .coherent_dma_mask = DMA_BIT_MASK(32), 778 }, 779 .resource = dove_sdio0_resources, 780 .num_resources = ARRAY_SIZE(dove_sdio0_resources), 781}; 782 783void __init dove_sdio0_init(void) 784{ 785 platform_device_register(&dove_sdio0); 786} 787 788static struct resource dove_sdio1_resources[] = { 789 { 790 .start = DOVE_SDIO1_PHYS_BASE, 791 .end = DOVE_SDIO1_PHYS_BASE + 0xff, 792 .flags = IORESOURCE_MEM, 793 }, { 794 .start = IRQ_DOVE_SDIO1, 795 .end = IRQ_DOVE_SDIO1, 796 .flags = IORESOURCE_IRQ, 797 }, 798}; 799 800static struct platform_device dove_sdio1 = { 801 .name = "sdhci-mv", 802 .id = 1, 803 .dev = { 804 .dma_mask = &sdio_dmamask, 805 .coherent_dma_mask = DMA_BIT_MASK(32), 806 }, 807 .resource = dove_sdio1_resources, 808 .num_resources = ARRAY_SIZE(dove_sdio1_resources), 809}; 810 811void __init dove_sdio1_init(void) 812{ 813 platform_device_register(&dove_sdio1); 814} 815 816void __init dove_init(void) 817{ 818 int tclk; 819 820 tclk = get_tclk(); 821 822 printk(KERN_INFO "Dove 88AP510 SoC, "); 823 printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000); 824 825#ifdef CONFIG_CACHE_TAUROS2 826 tauros2_init(); 827#endif 828 dove_setup_cpu_mbus(); 829 830 dove_ge00_shared_data.t_clk = tclk; 831 dove_uart0_data[0].uartclk = tclk; 832 dove_uart1_data[0].uartclk = tclk; 833 dove_uart2_data[0].uartclk = tclk; 834 dove_uart3_data[0].uartclk = tclk; 835 dove_spi0_data.tclk = tclk; 836 dove_spi1_data.tclk = tclk; 837 838 /* internal devices that every board has */ 839 dove_rtc_init(); 840 dove_xor0_init(); 841 dove_xor1_init(); 842} 843