1/* 2 * <mach/asp.h> - DaVinci Audio Serial Port support 3 */ 4#ifndef __ASM_ARCH_DAVINCI_ASP_H 5#define __ASM_ARCH_DAVINCI_ASP_H 6 7#include <mach/irqs.h> 8#include <mach/edma.h> 9 10/* Bases of dm644x and dm355 register banks */ 11#define DAVINCI_ASP0_BASE 0x01E02000 12#define DAVINCI_ASP1_BASE 0x01E04000 13 14/* Bases of dm365 register banks */ 15#define DAVINCI_DM365_ASP0_BASE 0x01D02000 16 17/* Bases of dm646x register banks */ 18#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 19#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 20 21/* Bases of da850/da830 McASP0 register banks */ 22#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 23 24/* Bases of da830 McASP1 register banks */ 25#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 26 27/* EDMA channels of dm644x and dm355 */ 28#define DAVINCI_DMA_ASP0_TX 2 29#define DAVINCI_DMA_ASP0_RX 3 30#define DAVINCI_DMA_ASP1_TX 8 31#define DAVINCI_DMA_ASP1_RX 9 32 33/* EDMA channels of dm646x */ 34#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 35#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 36#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 37 38/* EDMA channels of da850/da830 McASP0 */ 39#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 40#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 41 42/* EDMA channels of da830 McASP1 */ 43#define DAVINCI_DA830_DMA_MCASP1_AREVT 2 44#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 45 46/* Interrupts */ 47#define DAVINCI_ASP0_RX_INT IRQ_MBRINT 48#define DAVINCI_ASP0_TX_INT IRQ_MBXINT 49#define DAVINCI_ASP1_RX_INT IRQ_MBRINT 50#define DAVINCI_ASP1_TX_INT IRQ_MBXINT 51 52struct snd_platform_data { 53 u32 tx_dma_offset; 54 u32 rx_dma_offset; 55 enum dma_event_q asp_chan_q; /* event queue number for ASP channel */ 56 enum dma_event_q ram_chan_q; /* event queue number for RAM channel */ 57 unsigned int codec_fmt; 58 /* 59 * Allowing this is more efficient and eliminates left and right swaps 60 * caused by underruns, but will swap the left and right channels 61 * when compared to previous behavior. 62 */ 63 unsigned enable_channel_combine:1; 64 unsigned sram_size_playback; 65 unsigned sram_size_capture; 66 67 /* 68 * If McBSP peripheral gets the clock from an external pin, 69 * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR 70 * and MCBSP_CLKS. 71 * Depending on different hardware connections it is possible 72 * to use this setting to change the behaviour of McBSP 73 * driver. The dm365_clk_input_pin enum is available for dm365 74 */ 75 int clk_input_pin; 76 77 /* 78 * This flag works when both clock and FS are outputs for the cpu 79 * and makes clock more accurate (FS is not symmetrical and the 80 * clock is very fast. 81 * The clock becoming faster is named 82 * i2s continuous serial clock (I2S_SCK) and it is an externally 83 * visible bit clock. 84 * 85 * first line : WordSelect 86 * second line : ContinuousSerialClock 87 * third line: SerialData 88 * 89 * SYMMETRICAL APPROACH: 90 * _______________________ LEFT 91 * _| RIGHT |______________________| 92 * _ _ _ _ _ _ _ _ 93 * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_ 94 * _ _ _ _ _ _ _ _ 95 * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_ 96 * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ 97 * 98 * ACCURATE CLOCK APPROACH: 99 * ______________ LEFT 100 * _| RIGHT |_______________________________| 101 * _ _ _ _ _ _ _ _ _ 102 * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| | 103 * _ _ _ _ dummy cycles 104 * _/ \_ ... _/ \_/ \_ ... _/ \__________________ 105 * \_/ \_/ \_/ \_/ 106 * 107 */ 108 bool i2s_accurate_sck; 109 110 /* McASP specific fields */ 111 int tdm_slots; 112 u8 op_mode; 113 u8 num_serializer; 114 u8 *serial_dir; 115 u8 version; 116 u8 txnumevt; 117 u8 rxnumevt; 118}; 119 120enum { 121 MCASP_VERSION_1 = 0, /* DM646x */ 122 MCASP_VERSION_2, /* DA8xx/OMAPL1x */ 123}; 124 125enum dm365_clk_input_pin { 126 MCBSP_CLKR = 0, /* DM365 */ 127 MCBSP_CLKS, 128}; 129 130#define INACTIVE_MODE 0 131#define TX_MODE 1 132#define RX_MODE 2 133 134#define DAVINCI_MCASP_IIS_MODE 0 135#define DAVINCI_MCASP_DIT_MODE 1 136 137#endif /* __ASM_ARCH_DAVINCI_ASP_H */ 138