1/* 2 * TI DaVinci DM644x chip specific setup 3 * 4 * Author: Kevin Hilman, Deep Root Systems, LLC 5 * 6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 */ 11#include <linux/init.h> 12#include <linux/clk.h> 13#include <linux/serial_8250.h> 14#include <linux/platform_device.h> 15#include <linux/gpio.h> 16 17#include <asm/mach/map.h> 18 19#include <mach/dm644x.h> 20#include <mach/cputype.h> 21#include <mach/edma.h> 22#include <mach/irqs.h> 23#include <mach/psc.h> 24#include <mach/mux.h> 25#include <mach/time.h> 26#include <mach/serial.h> 27#include <mach/common.h> 28#include <mach/asp.h> 29 30#include "clock.h" 31#include "mux.h" 32 33/* 34 * Device specific clocks 35 */ 36#define DM644X_REF_FREQ 27000000 37 38static struct pll_data pll1_data = { 39 .num = 1, 40 .phys_base = DAVINCI_PLL1_BASE, 41}; 42 43static struct pll_data pll2_data = { 44 .num = 2, 45 .phys_base = DAVINCI_PLL2_BASE, 46}; 47 48static struct clk ref_clk = { 49 .name = "ref_clk", 50 .rate = DM644X_REF_FREQ, 51}; 52 53static struct clk pll1_clk = { 54 .name = "pll1", 55 .parent = &ref_clk, 56 .pll_data = &pll1_data, 57 .flags = CLK_PLL, 58}; 59 60static struct clk pll1_sysclk1 = { 61 .name = "pll1_sysclk1", 62 .parent = &pll1_clk, 63 .flags = CLK_PLL, 64 .div_reg = PLLDIV1, 65}; 66 67static struct clk pll1_sysclk2 = { 68 .name = "pll1_sysclk2", 69 .parent = &pll1_clk, 70 .flags = CLK_PLL, 71 .div_reg = PLLDIV2, 72}; 73 74static struct clk pll1_sysclk3 = { 75 .name = "pll1_sysclk3", 76 .parent = &pll1_clk, 77 .flags = CLK_PLL, 78 .div_reg = PLLDIV3, 79}; 80 81static struct clk pll1_sysclk5 = { 82 .name = "pll1_sysclk5", 83 .parent = &pll1_clk, 84 .flags = CLK_PLL, 85 .div_reg = PLLDIV5, 86}; 87 88static struct clk pll1_aux_clk = { 89 .name = "pll1_aux_clk", 90 .parent = &pll1_clk, 91 .flags = CLK_PLL | PRE_PLL, 92}; 93 94static struct clk pll1_sysclkbp = { 95 .name = "pll1_sysclkbp", 96 .parent = &pll1_clk, 97 .flags = CLK_PLL | PRE_PLL, 98 .div_reg = BPDIV 99}; 100 101static struct clk pll2_clk = { 102 .name = "pll2", 103 .parent = &ref_clk, 104 .pll_data = &pll2_data, 105 .flags = CLK_PLL, 106}; 107 108static struct clk pll2_sysclk1 = { 109 .name = "pll2_sysclk1", 110 .parent = &pll2_clk, 111 .flags = CLK_PLL, 112 .div_reg = PLLDIV1, 113}; 114 115static struct clk pll2_sysclk2 = { 116 .name = "pll2_sysclk2", 117 .parent = &pll2_clk, 118 .flags = CLK_PLL, 119 .div_reg = PLLDIV2, 120}; 121 122static struct clk pll2_sysclkbp = { 123 .name = "pll2_sysclkbp", 124 .parent = &pll2_clk, 125 .flags = CLK_PLL | PRE_PLL, 126 .div_reg = BPDIV 127}; 128 129static struct clk dsp_clk = { 130 .name = "dsp", 131 .parent = &pll1_sysclk1, 132 .lpsc = DAVINCI_LPSC_GEM, 133 .flags = PSC_DSP, 134 .usecount = 1, /* REVISIT how to disable? */ 135}; 136 137static struct clk arm_clk = { 138 .name = "arm", 139 .parent = &pll1_sysclk2, 140 .lpsc = DAVINCI_LPSC_ARM, 141 .flags = ALWAYS_ENABLED, 142}; 143 144static struct clk vicp_clk = { 145 .name = "vicp", 146 .parent = &pll1_sysclk2, 147 .lpsc = DAVINCI_LPSC_IMCOP, 148 .flags = PSC_DSP, 149 .usecount = 1, /* REVISIT how to disable? */ 150}; 151 152static struct clk vpss_master_clk = { 153 .name = "vpss_master", 154 .parent = &pll1_sysclk3, 155 .lpsc = DAVINCI_LPSC_VPSSMSTR, 156 .flags = CLK_PSC, 157}; 158 159static struct clk vpss_slave_clk = { 160 .name = "vpss_slave", 161 .parent = &pll1_sysclk3, 162 .lpsc = DAVINCI_LPSC_VPSSSLV, 163}; 164 165static struct clk uart0_clk = { 166 .name = "uart0", 167 .parent = &pll1_aux_clk, 168 .lpsc = DAVINCI_LPSC_UART0, 169}; 170 171static struct clk uart1_clk = { 172 .name = "uart1", 173 .parent = &pll1_aux_clk, 174 .lpsc = DAVINCI_LPSC_UART1, 175}; 176 177static struct clk uart2_clk = { 178 .name = "uart2", 179 .parent = &pll1_aux_clk, 180 .lpsc = DAVINCI_LPSC_UART2, 181}; 182 183static struct clk emac_clk = { 184 .name = "emac", 185 .parent = &pll1_sysclk5, 186 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, 187}; 188 189static struct clk i2c_clk = { 190 .name = "i2c", 191 .parent = &pll1_aux_clk, 192 .lpsc = DAVINCI_LPSC_I2C, 193}; 194 195static struct clk ide_clk = { 196 .name = "ide", 197 .parent = &pll1_sysclk5, 198 .lpsc = DAVINCI_LPSC_ATA, 199}; 200 201static struct clk asp_clk = { 202 .name = "asp0", 203 .parent = &pll1_sysclk5, 204 .lpsc = DAVINCI_LPSC_McBSP, 205}; 206 207static struct clk mmcsd_clk = { 208 .name = "mmcsd", 209 .parent = &pll1_sysclk5, 210 .lpsc = DAVINCI_LPSC_MMC_SD, 211}; 212 213static struct clk spi_clk = { 214 .name = "spi", 215 .parent = &pll1_sysclk5, 216 .lpsc = DAVINCI_LPSC_SPI, 217}; 218 219static struct clk gpio_clk = { 220 .name = "gpio", 221 .parent = &pll1_sysclk5, 222 .lpsc = DAVINCI_LPSC_GPIO, 223}; 224 225static struct clk usb_clk = { 226 .name = "usb", 227 .parent = &pll1_sysclk5, 228 .lpsc = DAVINCI_LPSC_USB, 229}; 230 231static struct clk vlynq_clk = { 232 .name = "vlynq", 233 .parent = &pll1_sysclk5, 234 .lpsc = DAVINCI_LPSC_VLYNQ, 235}; 236 237static struct clk aemif_clk = { 238 .name = "aemif", 239 .parent = &pll1_sysclk5, 240 .lpsc = DAVINCI_LPSC_AEMIF, 241}; 242 243static struct clk pwm0_clk = { 244 .name = "pwm0", 245 .parent = &pll1_aux_clk, 246 .lpsc = DAVINCI_LPSC_PWM0, 247}; 248 249static struct clk pwm1_clk = { 250 .name = "pwm1", 251 .parent = &pll1_aux_clk, 252 .lpsc = DAVINCI_LPSC_PWM1, 253}; 254 255static struct clk pwm2_clk = { 256 .name = "pwm2", 257 .parent = &pll1_aux_clk, 258 .lpsc = DAVINCI_LPSC_PWM2, 259}; 260 261static struct clk timer0_clk = { 262 .name = "timer0", 263 .parent = &pll1_aux_clk, 264 .lpsc = DAVINCI_LPSC_TIMER0, 265}; 266 267static struct clk timer1_clk = { 268 .name = "timer1", 269 .parent = &pll1_aux_clk, 270 .lpsc = DAVINCI_LPSC_TIMER1, 271}; 272 273static struct clk timer2_clk = { 274 .name = "timer2", 275 .parent = &pll1_aux_clk, 276 .lpsc = DAVINCI_LPSC_TIMER2, 277 .usecount = 1, /* REVISIT: why cant' this be disabled? */ 278}; 279 280static struct clk_lookup dm644x_clks[] = { 281 CLK(NULL, "ref", &ref_clk), 282 CLK(NULL, "pll1", &pll1_clk), 283 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), 284 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), 285 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), 286 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), 287 CLK(NULL, "pll1_aux", &pll1_aux_clk), 288 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), 289 CLK(NULL, "pll2", &pll2_clk), 290 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), 291 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), 292 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), 293 CLK(NULL, "dsp", &dsp_clk), 294 CLK(NULL, "arm", &arm_clk), 295 CLK(NULL, "vicp", &vicp_clk), 296 CLK(NULL, "vpss_master", &vpss_master_clk), 297 CLK(NULL, "vpss_slave", &vpss_slave_clk), 298 CLK(NULL, "arm", &arm_clk), 299 CLK(NULL, "uart0", &uart0_clk), 300 CLK(NULL, "uart1", &uart1_clk), 301 CLK(NULL, "uart2", &uart2_clk), 302 CLK("davinci_emac.1", NULL, &emac_clk), 303 CLK("i2c_davinci.1", NULL, &i2c_clk), 304 CLK("palm_bk3710", NULL, &ide_clk), 305 CLK("davinci-asp", NULL, &asp_clk), 306 CLK("davinci_mmc.0", NULL, &mmcsd_clk), 307 CLK(NULL, "spi", &spi_clk), 308 CLK(NULL, "gpio", &gpio_clk), 309 CLK(NULL, "usb", &usb_clk), 310 CLK(NULL, "vlynq", &vlynq_clk), 311 CLK(NULL, "aemif", &aemif_clk), 312 CLK(NULL, "pwm0", &pwm0_clk), 313 CLK(NULL, "pwm1", &pwm1_clk), 314 CLK(NULL, "pwm2", &pwm2_clk), 315 CLK(NULL, "timer0", &timer0_clk), 316 CLK(NULL, "timer1", &timer1_clk), 317 CLK("watchdog", NULL, &timer2_clk), 318 CLK(NULL, NULL, NULL), 319}; 320 321static struct emac_platform_data dm644x_emac_pdata = { 322 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, 323 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET, 324 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET, 325 .mdio_reg_offset = DM644X_EMAC_MDIO_OFFSET, 326 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE, 327 .version = EMAC_VERSION_1, 328}; 329 330static struct resource dm644x_emac_resources[] = { 331 { 332 .start = DM644X_EMAC_BASE, 333 .end = DM644X_EMAC_BASE + 0x47ff, 334 .flags = IORESOURCE_MEM, 335 }, 336 { 337 .start = IRQ_EMACINT, 338 .end = IRQ_EMACINT, 339 .flags = IORESOURCE_IRQ, 340 }, 341}; 342 343static struct platform_device dm644x_emac_device = { 344 .name = "davinci_emac", 345 .id = 1, 346 .dev = { 347 .platform_data = &dm644x_emac_pdata, 348 }, 349 .num_resources = ARRAY_SIZE(dm644x_emac_resources), 350 .resource = dm644x_emac_resources, 351}; 352 353/* 354 * Device specific mux setup 355 * 356 * soc description mux mode mode mux dbg 357 * reg offset mask mode 358 */ 359static const struct mux_config dm644x_pins[] = { 360#ifdef CONFIG_DAVINCI_MUX 361MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true) 362MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true) 363MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) 364 365MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true) 366 367MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true) 368MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true) 369MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true) 370MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true) 371MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true) 372MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true) 373 374MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false) 375 376MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false) 377 378MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false) 379 380MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true) 381MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true) 382 383MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false) 384 385MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false) 386 387MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false) 388 389MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false) 390MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false) 391MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false) 392 393MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true) 394 395MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true) 396 397MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true) 398MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false) 399MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false) 400MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true) 401 402MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true) 403 404MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true) 405MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) 406#endif 407}; 408 409/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ 410static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = { 411 [IRQ_VDINT0] = 2, 412 [IRQ_VDINT1] = 6, 413 [IRQ_VDINT2] = 6, 414 [IRQ_HISTINT] = 6, 415 [IRQ_H3AINT] = 6, 416 [IRQ_PRVUINT] = 6, 417 [IRQ_RSZINT] = 6, 418 [7] = 7, 419 [IRQ_VENCINT] = 6, 420 [IRQ_ASQINT] = 6, 421 [IRQ_IMXINT] = 6, 422 [IRQ_VLCDINT] = 6, 423 [IRQ_USBINT] = 4, 424 [IRQ_EMACINT] = 4, 425 [14] = 7, 426 [15] = 7, 427 [IRQ_CCINT0] = 5, /* dma */ 428 [IRQ_CCERRINT] = 5, /* dma */ 429 [IRQ_TCERRINT0] = 5, /* dma */ 430 [IRQ_TCERRINT] = 5, /* dma */ 431 [IRQ_PSCIN] = 7, 432 [21] = 7, 433 [IRQ_IDE] = 4, 434 [23] = 7, 435 [IRQ_MBXINT] = 7, 436 [IRQ_MBRINT] = 7, 437 [IRQ_MMCINT] = 7, 438 [IRQ_SDIOINT] = 7, 439 [28] = 7, 440 [IRQ_DDRINT] = 7, 441 [IRQ_AEMIFINT] = 7, 442 [IRQ_VLQINT] = 4, 443 [IRQ_TINT0_TINT12] = 2, /* clockevent */ 444 [IRQ_TINT0_TINT34] = 2, /* clocksource */ 445 [IRQ_TINT1_TINT12] = 7, /* DSP timer */ 446 [IRQ_TINT1_TINT34] = 7, /* system tick */ 447 [IRQ_PWMINT0] = 7, 448 [IRQ_PWMINT1] = 7, 449 [IRQ_PWMINT2] = 7, 450 [IRQ_I2C] = 3, 451 [IRQ_UARTINT0] = 3, 452 [IRQ_UARTINT1] = 3, 453 [IRQ_UARTINT2] = 3, 454 [IRQ_SPINT0] = 3, 455 [IRQ_SPINT1] = 3, 456 [45] = 7, 457 [IRQ_DSP2ARM0] = 4, 458 [IRQ_DSP2ARM1] = 4, 459 [IRQ_GPIO0] = 7, 460 [IRQ_GPIO1] = 7, 461 [IRQ_GPIO2] = 7, 462 [IRQ_GPIO3] = 7, 463 [IRQ_GPIO4] = 7, 464 [IRQ_GPIO5] = 7, 465 [IRQ_GPIO6] = 7, 466 [IRQ_GPIO7] = 7, 467 [IRQ_GPIOBNK0] = 7, 468 [IRQ_GPIOBNK1] = 7, 469 [IRQ_GPIOBNK2] = 7, 470 [IRQ_GPIOBNK3] = 7, 471 [IRQ_GPIOBNK4] = 7, 472 [IRQ_COMMTX] = 7, 473 [IRQ_COMMRX] = 7, 474 [IRQ_EMUINT] = 7, 475}; 476 477/*----------------------------------------------------------------------*/ 478 479static const s8 480queue_tc_mapping[][2] = { 481 /* {event queue no, TC no} */ 482 {0, 0}, 483 {1, 1}, 484 {-1, -1}, 485}; 486 487static const s8 488queue_priority_mapping[][2] = { 489 /* {event queue no, Priority} */ 490 {0, 3}, 491 {1, 7}, 492 {-1, -1}, 493}; 494 495static struct edma_soc_info edma_cc0_info = { 496 .n_channel = 64, 497 .n_region = 4, 498 .n_slot = 128, 499 .n_tc = 2, 500 .n_cc = 1, 501 .queue_tc_mapping = queue_tc_mapping, 502 .queue_priority_mapping = queue_priority_mapping, 503}; 504 505static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = { 506 &edma_cc0_info, 507}; 508 509static struct resource edma_resources[] = { 510 { 511 .name = "edma_cc0", 512 .start = 0x01c00000, 513 .end = 0x01c00000 + SZ_64K - 1, 514 .flags = IORESOURCE_MEM, 515 }, 516 { 517 .name = "edma_tc0", 518 .start = 0x01c10000, 519 .end = 0x01c10000 + SZ_1K - 1, 520 .flags = IORESOURCE_MEM, 521 }, 522 { 523 .name = "edma_tc1", 524 .start = 0x01c10400, 525 .end = 0x01c10400 + SZ_1K - 1, 526 .flags = IORESOURCE_MEM, 527 }, 528 { 529 .name = "edma0", 530 .start = IRQ_CCINT0, 531 .flags = IORESOURCE_IRQ, 532 }, 533 { 534 .name = "edma0_err", 535 .start = IRQ_CCERRINT, 536 .flags = IORESOURCE_IRQ, 537 }, 538 /* not using TC*_ERR */ 539}; 540 541static struct platform_device dm644x_edma_device = { 542 .name = "edma", 543 .id = 0, 544 .dev.platform_data = dm644x_edma_info, 545 .num_resources = ARRAY_SIZE(edma_resources), 546 .resource = edma_resources, 547}; 548 549/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */ 550static struct resource dm644x_asp_resources[] = { 551 { 552 .start = DAVINCI_ASP0_BASE, 553 .end = DAVINCI_ASP0_BASE + SZ_8K - 1, 554 .flags = IORESOURCE_MEM, 555 }, 556 { 557 .start = DAVINCI_DMA_ASP0_TX, 558 .end = DAVINCI_DMA_ASP0_TX, 559 .flags = IORESOURCE_DMA, 560 }, 561 { 562 .start = DAVINCI_DMA_ASP0_RX, 563 .end = DAVINCI_DMA_ASP0_RX, 564 .flags = IORESOURCE_DMA, 565 }, 566}; 567 568static struct platform_device dm644x_asp_device = { 569 .name = "davinci-asp", 570 .id = -1, 571 .num_resources = ARRAY_SIZE(dm644x_asp_resources), 572 .resource = dm644x_asp_resources, 573}; 574 575static struct resource dm644x_vpss_resources[] = { 576 { 577 /* VPSS Base address */ 578 .name = "vpss", 579 .start = 0x01c73400, 580 .end = 0x01c73400 + 0xff, 581 .flags = IORESOURCE_MEM, 582 }, 583}; 584 585static struct platform_device dm644x_vpss_device = { 586 .name = "vpss", 587 .id = -1, 588 .dev.platform_data = "dm644x_vpss", 589 .num_resources = ARRAY_SIZE(dm644x_vpss_resources), 590 .resource = dm644x_vpss_resources, 591}; 592 593static struct resource vpfe_resources[] = { 594 { 595 .start = IRQ_VDINT0, 596 .end = IRQ_VDINT0, 597 .flags = IORESOURCE_IRQ, 598 }, 599 { 600 .start = IRQ_VDINT1, 601 .end = IRQ_VDINT1, 602 .flags = IORESOURCE_IRQ, 603 }, 604}; 605 606static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); 607static struct resource dm644x_ccdc_resource[] = { 608 /* CCDC Base address */ 609 { 610 .start = 0x01c70400, 611 .end = 0x01c70400 + 0xff, 612 .flags = IORESOURCE_MEM, 613 }, 614}; 615 616static struct platform_device dm644x_ccdc_dev = { 617 .name = "dm644x_ccdc", 618 .id = -1, 619 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource), 620 .resource = dm644x_ccdc_resource, 621 .dev = { 622 .dma_mask = &vpfe_capture_dma_mask, 623 .coherent_dma_mask = DMA_BIT_MASK(32), 624 }, 625}; 626 627static struct platform_device vpfe_capture_dev = { 628 .name = CAPTURE_DRV_NAME, 629 .id = -1, 630 .num_resources = ARRAY_SIZE(vpfe_resources), 631 .resource = vpfe_resources, 632 .dev = { 633 .dma_mask = &vpfe_capture_dma_mask, 634 .coherent_dma_mask = DMA_BIT_MASK(32), 635 }, 636}; 637 638void dm644x_set_vpfe_config(struct vpfe_config *cfg) 639{ 640 vpfe_capture_dev.dev.platform_data = cfg; 641} 642 643/*----------------------------------------------------------------------*/ 644 645static struct map_desc dm644x_io_desc[] = { 646 { 647 .virtual = IO_VIRT, 648 .pfn = __phys_to_pfn(IO_PHYS), 649 .length = IO_SIZE, 650 .type = MT_DEVICE 651 }, 652 { 653 .virtual = SRAM_VIRT, 654 .pfn = __phys_to_pfn(0x00008000), 655 .length = SZ_16K, 656 .type = MT_MEMORY_NONCACHED, 657 }, 658}; 659 660/* Contents of JTAG ID register used to identify exact cpu type */ 661static struct davinci_id dm644x_ids[] = { 662 { 663 .variant = 0x0, 664 .part_no = 0xb700, 665 .manufacturer = 0x017, 666 .cpu_id = DAVINCI_CPU_ID_DM6446, 667 .name = "dm6446", 668 }, 669 { 670 .variant = 0x1, 671 .part_no = 0xb700, 672 .manufacturer = 0x017, 673 .cpu_id = DAVINCI_CPU_ID_DM6446, 674 .name = "dm6446a", 675 }, 676}; 677 678static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; 679 680/* 681 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers 682 * T0_TOP: Timer 0, top : clocksource for generic timekeeping 683 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) 684 * T1_TOP: Timer 1, top : <unused> 685 */ 686static struct davinci_timer_info dm644x_timer_info = { 687 .timers = davinci_timer_instance, 688 .clockevent_id = T0_BOT, 689 .clocksource_id = T0_TOP, 690}; 691 692static struct plat_serial8250_port dm644x_serial_platform_data[] = { 693 { 694 .mapbase = DAVINCI_UART0_BASE, 695 .irq = IRQ_UARTINT0, 696 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 697 UPF_IOREMAP, 698 .iotype = UPIO_MEM, 699 .regshift = 2, 700 }, 701 { 702 .mapbase = DAVINCI_UART1_BASE, 703 .irq = IRQ_UARTINT1, 704 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 705 UPF_IOREMAP, 706 .iotype = UPIO_MEM, 707 .regshift = 2, 708 }, 709 { 710 .mapbase = DAVINCI_UART2_BASE, 711 .irq = IRQ_UARTINT2, 712 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 713 UPF_IOREMAP, 714 .iotype = UPIO_MEM, 715 .regshift = 2, 716 }, 717 { 718 .flags = 0 719 }, 720}; 721 722static struct platform_device dm644x_serial_device = { 723 .name = "serial8250", 724 .id = PLAT8250_DEV_PLATFORM, 725 .dev = { 726 .platform_data = dm644x_serial_platform_data, 727 }, 728}; 729 730static struct davinci_soc_info davinci_soc_info_dm644x = { 731 .io_desc = dm644x_io_desc, 732 .io_desc_num = ARRAY_SIZE(dm644x_io_desc), 733 .jtag_id_reg = 0x01c40028, 734 .ids = dm644x_ids, 735 .ids_num = ARRAY_SIZE(dm644x_ids), 736 .cpu_clks = dm644x_clks, 737 .psc_bases = dm644x_psc_bases, 738 .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), 739 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, 740 .pinmux_pins = dm644x_pins, 741 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), 742 .intc_base = DAVINCI_ARM_INTC_BASE, 743 .intc_type = DAVINCI_INTC_TYPE_AINTC, 744 .intc_irq_prios = dm644x_default_priorities, 745 .intc_irq_num = DAVINCI_N_AINTC_IRQ, 746 .timer_info = &dm644x_timer_info, 747 .gpio_type = GPIO_TYPE_DAVINCI, 748 .gpio_base = DAVINCI_GPIO_BASE, 749 .gpio_num = 71, 750 .gpio_irq = IRQ_GPIOBNK0, 751 .serial_dev = &dm644x_serial_device, 752 .emac_pdata = &dm644x_emac_pdata, 753 .sram_dma = 0x00008000, 754 .sram_len = SZ_16K, 755 .reset_device = &davinci_wdt_device, 756}; 757 758void __init dm644x_init_asp(struct snd_platform_data *pdata) 759{ 760 davinci_cfg_reg(DM644X_MCBSP); 761 dm644x_asp_device.dev.platform_data = pdata; 762 platform_device_register(&dm644x_asp_device); 763} 764 765void __init dm644x_init(void) 766{ 767 davinci_common_init(&davinci_soc_info_dm644x); 768} 769 770static int __init dm644x_init_devices(void) 771{ 772 if (!cpu_is_davinci_dm644x()) 773 return 0; 774 775 /* Add ccdc clock aliases */ 776 clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL); 777 clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL); 778 platform_device_register(&dm644x_edma_device); 779 platform_device_register(&dm644x_emac_device); 780 platform_device_register(&dm644x_vpss_device); 781 platform_device_register(&dm644x_ccdc_dev); 782 platform_device_register(&vpfe_capture_dev); 783 784 return 0; 785} 786postcore_initcall(dm644x_init_devices); 787