1#ifndef ASMARM_PCI_H 2#define ASMARM_PCI_H 3 4#ifdef __KERNEL__ 5#include <asm-generic/pci-dma-compat.h> 6 7#include <asm/mach/pci.h> /* for pci_sys_data */ 8#include <mach/hardware.h> /* for PCIBIOS_MIN_* */ 9 10#ifdef CONFIG_PCI_DOMAINS 11static inline int pci_domain_nr(struct pci_bus *bus) 12{ 13 struct pci_sys_data *root = bus->sysdata; 14 15 return root->domain; 16} 17 18static inline int pci_proc_domain(struct pci_bus *bus) 19{ 20 return pci_domain_nr(bus); 21} 22#endif /* CONFIG_PCI_DOMAINS */ 23 24#ifdef CONFIG_PCI_HOST_ITE8152 25/* ITE bridge requires setting latency timer to avoid early bus access 26 termination by PIC bus mater devices 27*/ 28extern void pcibios_set_master(struct pci_dev *dev); 29#else 30static inline void pcibios_set_master(struct pci_dev *dev) 31{ 32 /* No special bus mastering setup handling */ 33} 34#endif 35 36static inline void pcibios_penalize_isa_irq(int irq, int active) 37{ 38 /* We don't do dynamic PCI IRQ allocation */ 39} 40 41/* 42 * The PCI address space does equal the physical memory address space. 43 * The networking and block device layers use this boolean for bounce 44 * buffer decisions. 45 */ 46#define PCI_DMA_BUS_IS_PHYS (1) 47 48#ifdef CONFIG_PCI 49static inline void pci_dma_burst_advice(struct pci_dev *pdev, 50 enum pci_dma_burst_strategy *strat, 51 unsigned long *strategy_parameter) 52{ 53 *strat = PCI_DMA_BURST_INFINITY; 54 *strategy_parameter = ~0UL; 55} 56#endif 57 58#define HAVE_PCI_MMAP 59extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 60 enum pci_mmap_state mmap_state, int write_combine); 61 62extern void 63pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 64 struct resource *res); 65 66extern void 67pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 68 struct pci_bus_region *region); 69 70/* 71 * Dummy implementation; always return 0. 72 */ 73static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 74{ 75 return 0; 76} 77 78#endif /* __KERNEL__ */ 79 80#endif 81