1/* 2 * linux/arch/arm/include/asm/hardware/coresight.h 3 * 4 * CoreSight components' registers 5 * 6 * Copyright (C) 2009 Nokia Corporation. 7 * Alexander Shishkin 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14#ifndef __ASM_HARDWARE_CORESIGHT_H 15#define __ASM_HARDWARE_CORESIGHT_H 16 17#define TRACER_ACCESSED_BIT 0 18#define TRACER_RUNNING_BIT 1 19#define TRACER_CYCLE_ACC_BIT 2 20#define TRACER_ACCESSED BIT(TRACER_ACCESSED_BIT) 21#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT) 22#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT) 23 24struct tracectx { 25 unsigned int etb_bufsz; 26 void __iomem *etb_regs; 27 void __iomem *etm_regs; 28 unsigned long flags; 29 int ncmppairs; 30 int etm_portsz; 31 struct device *dev; 32 struct clk *emu_clk; 33 struct mutex mutex; 34}; 35 36#define TRACER_TIMEOUT 10000 37 38#define etm_writel(t, v, x) \ 39 (__raw_writel((v), (t)->etm_regs + (x))) 40#define etm_readl(t, x) (__raw_readl((t)->etm_regs + (x))) 41 42/* CoreSight Management Registers */ 43#define CSMR_LOCKACCESS 0xfb0 44#define CSMR_LOCKSTATUS 0xfb4 45#define CSMR_AUTHSTATUS 0xfb8 46#define CSMR_DEVID 0xfc8 47#define CSMR_DEVTYPE 0xfcc 48/* CoreSight Component Registers */ 49#define CSCR_CLASS 0xff4 50 51#define UNLOCK_MAGIC 0xc5acce55 52 53/* ETM control register, "ETM Architecture", 3.3.1 */ 54#define ETMR_CTRL 0 55#define ETMCTRL_POWERDOWN 1 56#define ETMCTRL_PROGRAM (1 << 10) 57#define ETMCTRL_PORTSEL (1 << 11) 58#define ETMCTRL_DO_CONTEXTID (3 << 14) 59#define ETMCTRL_PORTMASK1 (7 << 4) 60#define ETMCTRL_PORTMASK2 (1 << 21) 61#define ETMCTRL_PORTMASK (ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2) 62#define ETMCTRL_PORTSIZE(x) ((((x) & 7) << 4) | (!!((x) & 8)) << 21) 63#define ETMCTRL_DO_CPRT (1 << 1) 64#define ETMCTRL_DATAMASK (3 << 2) 65#define ETMCTRL_DATA_DO_DATA (1 << 2) 66#define ETMCTRL_DATA_DO_ADDR (1 << 3) 67#define ETMCTRL_DATA_DO_BOTH (ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR) 68#define ETMCTRL_BRANCH_OUTPUT (1 << 8) 69#define ETMCTRL_CYCLEACCURATE (1 << 12) 70 71/* ETM configuration code register */ 72#define ETMR_CONFCODE (0x04) 73 74/* ETM trace start/stop resource control register */ 75#define ETMR_TRACESSCTRL (0x18) 76 77/* ETM trigger event register */ 78#define ETMR_TRIGEVT (0x08) 79 80/* address access type register bits, "ETM architecture", 81 * table 3-27 */ 82/* - access type */ 83#define ETMAAT_IFETCH 0 84#define ETMAAT_IEXEC 1 85#define ETMAAT_IEXECPASS 2 86#define ETMAAT_IEXECFAIL 3 87#define ETMAAT_DLOADSTORE 4 88#define ETMAAT_DLOAD 5 89#define ETMAAT_DSTORE 6 90/* - comparison access size */ 91#define ETMAAT_JAVA (0 << 3) 92#define ETMAAT_THUMB (1 << 3) 93#define ETMAAT_ARM (3 << 3) 94/* - data value comparison control */ 95#define ETMAAT_NOVALCMP (0 << 5) 96#define ETMAAT_VALMATCH (1 << 5) 97#define ETMAAT_VALNOMATCH (3 << 5) 98/* - exact match */ 99#define ETMAAT_EXACTMATCH (1 << 7) 100/* - context id comparator control */ 101#define ETMAAT_IGNCONTEXTID (0 << 8) 102#define ETMAAT_VALUE1 (1 << 8) 103#define ETMAAT_VALUE2 (2 << 8) 104#define ETMAAT_VALUE3 (3 << 8) 105/* - security level control */ 106#define ETMAAT_IGNSECURITY (0 << 10) 107#define ETMAAT_NSONLY (1 << 10) 108#define ETMAAT_SONLY (2 << 10) 109 110#define ETMR_COMP_VAL(x) (0x40 + (x) * 4) 111#define ETMR_COMP_ACC_TYPE(x) (0x80 + (x) * 4) 112 113/* ETM status register, "ETM Architecture", 3.3.2 */ 114#define ETMR_STATUS (0x10) 115#define ETMST_OVERFLOW (1 << 0) 116#define ETMST_PROGBIT (1 << 1) 117#define ETMST_STARTSTOP (1 << 2) 118#define ETMST_TRIGGER (1 << 3) 119 120#define etm_progbit(t) (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT) 121#define etm_started(t) (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP) 122#define etm_triggered(t) (etm_readl((t), ETMR_STATUS) & ETMST_TRIGGER) 123 124#define ETMR_TRACEENCTRL2 0x1c 125#define ETMR_TRACEENCTRL 0x24 126#define ETMTE_INCLEXCL (1 << 24) 127#define ETMR_TRACEENEVT 0x20 128#define ETMCTRL_OPTS (ETMCTRL_DO_CPRT | \ 129 ETMCTRL_DATA_DO_ADDR | \ 130 ETMCTRL_BRANCH_OUTPUT | \ 131 ETMCTRL_DO_CONTEXTID) 132 133/* ETM management registers, "ETM Architecture", 3.5.24 */ 134#define ETMMR_OSLAR 0x300 135#define ETMMR_OSLSR 0x304 136#define ETMMR_OSSRR 0x308 137#define ETMMR_PDSR 0x314 138 139/* ETB registers, "CoreSight Components TRM", 9.3 */ 140#define ETBR_DEPTH 0x04 141#define ETBR_STATUS 0x0c 142#define ETBR_READMEM 0x10 143#define ETBR_READADDR 0x14 144#define ETBR_WRITEADDR 0x18 145#define ETBR_TRIGGERCOUNT 0x1c 146#define ETBR_CTRL 0x20 147#define ETBR_FORMATTERCTRL 0x304 148#define ETBFF_ENFTC 1 149#define ETBFF_ENFCONT (1 << 1) 150#define ETBFF_FONFLIN (1 << 4) 151#define ETBFF_MANUAL_FLUSH (1 << 6) 152#define ETBFF_TRIGIN (1 << 8) 153#define ETBFF_TRIGEVT (1 << 9) 154#define ETBFF_TRIGFL (1 << 10) 155 156#define etb_writel(t, v, x) \ 157 (__raw_writel((v), (t)->etb_regs + (x))) 158#define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x))) 159 160#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0) 161#define etm_unlock(t) \ 162 do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0) 163 164#define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0) 165#define etb_unlock(t) \ 166 do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0) 167 168#endif /* __ASM_HARDWARE_CORESIGHT_H */ 169