1#ifndef __ALPHA_TSUNAMI__H__ 2#define __ALPHA_TSUNAMI__H__ 3 4#include <linux/types.h> 5#include <asm/compiler.h> 6 7/* 8 * TSUNAMI/TYPHOON are the internal names for the core logic chipset which 9 * provides memory controller and PCI access for the 21264 based systems. 10 * 11 * This file is based on: 12 * 13 * Tsunami System Programmers Manual 14 * Preliminary, Chapters 2-5 15 * 16 */ 17 18#ifdef USE_48_BIT_KSEG 19#define TS_BIAS 0x80000000000UL 20#else 21#define TS_BIAS 0x10000000000UL 22#endif 23 24/* 25 * CChip, DChip, and PChip registers 26 */ 27 28typedef struct { 29 volatile unsigned long csr __attribute__((aligned(64))); 30} tsunami_64; 31 32typedef struct { 33 tsunami_64 csc; 34 tsunami_64 mtr; 35 tsunami_64 misc; 36 tsunami_64 mpd; 37 tsunami_64 aar0; 38 tsunami_64 aar1; 39 tsunami_64 aar2; 40 tsunami_64 aar3; 41 tsunami_64 dim0; 42 tsunami_64 dim1; 43 tsunami_64 dir0; 44 tsunami_64 dir1; 45 tsunami_64 drir; 46 tsunami_64 prben; 47 tsunami_64 iic; /* a.k.a. iic0 */ 48 tsunami_64 wdr; /* a.k.a. iic1 */ 49 tsunami_64 mpr0; 50 tsunami_64 mpr1; 51 tsunami_64 mpr2; 52 tsunami_64 mpr3; 53 tsunami_64 mctl; 54 tsunami_64 __pad1; 55 tsunami_64 ttr; 56 tsunami_64 tdr; 57 tsunami_64 dim2; 58 tsunami_64 dim3; 59 tsunami_64 dir2; 60 tsunami_64 dir3; 61 tsunami_64 iic2; 62 tsunami_64 iic3; 63} tsunami_cchip; 64 65typedef struct { 66 tsunami_64 dsc; 67 tsunami_64 str; 68 tsunami_64 drev; 69} tsunami_dchip; 70 71typedef struct { 72 tsunami_64 wsba[4]; 73 tsunami_64 wsm[4]; 74 tsunami_64 tba[4]; 75 tsunami_64 pctl; 76 tsunami_64 plat; 77 tsunami_64 reserved; 78 tsunami_64 perror; 79 tsunami_64 perrmask; 80 tsunami_64 perrset; 81 tsunami_64 tlbiv; 82 tsunami_64 tlbia; 83 tsunami_64 pmonctl; 84 tsunami_64 pmoncnt; 85} tsunami_pchip; 86 87#define TSUNAMI_cchip ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL)) 88#define TSUNAMI_dchip ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL)) 89#define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL)) 90#define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL)) 91extern int TSUNAMI_bootcpu; 92 93/* 94 * TSUNAMI Pchip Error register. 95 */ 96 97#define perror_m_lost 0x1 98#define perror_m_serr 0x2 99#define perror_m_perr 0x4 100#define perror_m_dcrto 0x8 101#define perror_m_sge 0x10 102#define perror_m_ape 0x20 103#define perror_m_ta 0x40 104#define perror_m_rdpe 0x80 105#define perror_m_nds 0x100 106#define perror_m_rto 0x200 107#define perror_m_uecc 0x400 108#define perror_m_cre 0x800 109#define perror_m_addrl 0xFFFFFFFF0000UL 110#define perror_m_addrh 0x7000000000000UL 111#define perror_m_cmd 0xF0000000000000UL 112#define perror_m_syn 0xFF00000000000000UL 113union TPchipPERROR { 114 struct { 115 unsigned int perror_v_lost : 1; 116 unsigned perror_v_serr : 1; 117 unsigned perror_v_perr : 1; 118 unsigned perror_v_dcrto : 1; 119 unsigned perror_v_sge : 1; 120 unsigned perror_v_ape : 1; 121 unsigned perror_v_ta : 1; 122 unsigned perror_v_rdpe : 1; 123 unsigned perror_v_nds : 1; 124 unsigned perror_v_rto : 1; 125 unsigned perror_v_uecc : 1; 126 unsigned perror_v_cre : 1; 127 unsigned perror_v_rsvd1 : 4; 128 unsigned perror_v_addrl : 32; 129 unsigned perror_v_addrh : 3; 130 unsigned perror_v_rsvd2 : 1; 131 unsigned perror_v_cmd : 4; 132 unsigned perror_v_syn : 8; 133 } perror_r_bits; 134 int perror_q_whole [2]; 135}; 136 137/* 138 * TSUNAMI Pchip Window Space Base Address register. 139 */ 140#define wsba_m_ena 0x1 141#define wsba_m_sg 0x2 142#define wsba_m_ptp 0x4 143#define wsba_m_addr 0xFFF00000 144#define wmask_k_sz1gb 0x3FF00000 145union TPchipWSBA { 146 struct { 147 unsigned wsba_v_ena : 1; 148 unsigned wsba_v_sg : 1; 149 unsigned wsba_v_ptp : 1; 150 unsigned wsba_v_rsvd1 : 17; 151 unsigned wsba_v_addr : 12; 152 unsigned wsba_v_rsvd2 : 32; 153 } wsba_r_bits; 154 int wsba_q_whole [2]; 155}; 156 157/* 158 * TSUNAMI Pchip Control Register 159 */ 160#define pctl_m_fdsc 0x1 161#define pctl_m_fbtb 0x2 162#define pctl_m_thdis 0x4 163#define pctl_m_chaindis 0x8 164#define pctl_m_tgtlat 0x10 165#define pctl_m_hole 0x20 166#define pctl_m_mwin 0x40 167#define pctl_m_arbena 0x80 168#define pctl_m_prigrp 0x7F00 169#define pctl_m_ppri 0x8000 170#define pctl_m_rsvd1 0x30000 171#define pctl_m_eccen 0x40000 172#define pctl_m_padm 0x80000 173#define pctl_m_cdqmax 0xF00000 174#define pctl_m_rev 0xFF000000 175#define pctl_m_crqmax 0xF00000000UL 176#define pctl_m_ptpmax 0xF000000000UL 177#define pctl_m_pclkx 0x30000000000UL 178#define pctl_m_fdsdis 0x40000000000UL 179#define pctl_m_fdwdis 0x80000000000UL 180#define pctl_m_ptevrfy 0x100000000000UL 181#define pctl_m_rpp 0x200000000000UL 182#define pctl_m_pid 0xC00000000000UL 183#define pctl_m_rsvd2 0xFFFF000000000000UL 184 185union TPchipPCTL { 186 struct { 187 unsigned pctl_v_fdsc : 1; 188 unsigned pctl_v_fbtb : 1; 189 unsigned pctl_v_thdis : 1; 190 unsigned pctl_v_chaindis : 1; 191 unsigned pctl_v_tgtlat : 1; 192 unsigned pctl_v_hole : 1; 193 unsigned pctl_v_mwin : 1; 194 unsigned pctl_v_arbena : 1; 195 unsigned pctl_v_prigrp : 7; 196 unsigned pctl_v_ppri : 1; 197 unsigned pctl_v_rsvd1 : 2; 198 unsigned pctl_v_eccen : 1; 199 unsigned pctl_v_padm : 1; 200 unsigned pctl_v_cdqmax : 4; 201 unsigned pctl_v_rev : 8; 202 unsigned pctl_v_crqmax : 4; 203 unsigned pctl_v_ptpmax : 4; 204 unsigned pctl_v_pclkx : 2; 205 unsigned pctl_v_fdsdis : 1; 206 unsigned pctl_v_fdwdis : 1; 207 unsigned pctl_v_ptevrfy : 1; 208 unsigned pctl_v_rpp : 1; 209 unsigned pctl_v_pid : 2; 210 unsigned pctl_v_rsvd2 : 16; 211 } pctl_r_bits; 212 int pctl_q_whole [2]; 213}; 214 215/* 216 * TSUNAMI Pchip Error Mask Register. 217 */ 218#define perrmask_m_lost 0x1 219#define perrmask_m_serr 0x2 220#define perrmask_m_perr 0x4 221#define perrmask_m_dcrto 0x8 222#define perrmask_m_sge 0x10 223#define perrmask_m_ape 0x20 224#define perrmask_m_ta 0x40 225#define perrmask_m_rdpe 0x80 226#define perrmask_m_nds 0x100 227#define perrmask_m_rto 0x200 228#define perrmask_m_uecc 0x400 229#define perrmask_m_cre 0x800 230#define perrmask_m_rsvd 0xFFFFFFFFFFFFF000UL 231union TPchipPERRMASK { 232 struct { 233 unsigned int perrmask_v_lost : 1; 234 unsigned perrmask_v_serr : 1; 235 unsigned perrmask_v_perr : 1; 236 unsigned perrmask_v_dcrto : 1; 237 unsigned perrmask_v_sge : 1; 238 unsigned perrmask_v_ape : 1; 239 unsigned perrmask_v_ta : 1; 240 unsigned perrmask_v_rdpe : 1; 241 unsigned perrmask_v_nds : 1; 242 unsigned perrmask_v_rto : 1; 243 unsigned perrmask_v_uecc : 1; 244 unsigned perrmask_v_cre : 1; 245 unsigned perrmask_v_rsvd1 : 20; 246 unsigned perrmask_v_rsvd2 : 32; 247 } perrmask_r_bits; 248 int perrmask_q_whole [2]; 249}; 250 251/* 252 * Memory spaces: 253 */ 254#define TSUNAMI_HOSE(h) (((unsigned long)(h)) << 33) 255#define TSUNAMI_BASE (IDENT_ADDR + TS_BIAS) 256 257#define TSUNAMI_MEM(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x000000000UL) 258#define _TSUNAMI_IACK_SC(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1F8000000UL) 259#define TSUNAMI_IO(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FC000000UL) 260#define TSUNAMI_CONF(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FE000000UL) 261 262#define TSUNAMI_IACK_SC _TSUNAMI_IACK_SC(0) /* hack! */ 263 264 265/* 266 * The canonical non-remaped I/O and MEM addresses have these values 267 * subtracted out. This is arranged so that folks manipulating ISA 268 * devices can use their familiar numbers and have them map to bus 0. 269 */ 270 271#define TSUNAMI_IO_BIAS TSUNAMI_IO(0) 272#define TSUNAMI_MEM_BIAS TSUNAMI_MEM(0) 273 274/* The IO address space is larger than 0xffff */ 275#define TSUNAMI_IO_SPACE (TSUNAMI_CONF(0) - TSUNAMI_IO(0)) 276 277/* Offset between ram physical addresses and pci64 DAC bus addresses. */ 278#define TSUNAMI_DAC_OFFSET (1UL << 40) 279 280/* 281 * Data structure for handling TSUNAMI machine checks: 282 */ 283struct el_TSUNAMI_sysdata_mcheck { 284}; 285 286 287#ifdef __KERNEL__ 288 289#ifndef __EXTERN_INLINE 290#define __EXTERN_INLINE extern inline 291#define __IO_EXTERN_INLINE 292#endif 293 294/* 295 * I/O functions: 296 * 297 * TSUNAMI, the 21??? PCI/memory support chipset for the EV6 (21264) 298 * can only use linear accesses to get at PCI memory and I/O spaces. 299 */ 300 301/* 302 * Memory functions. all accesses are done through linear space. 303 */ 304extern void __iomem *tsunami_ioportmap(unsigned long addr); 305extern void __iomem *tsunami_ioremap(unsigned long addr, unsigned long size); 306__EXTERN_INLINE int tsunami_is_ioaddr(unsigned long addr) 307{ 308 return addr >= TSUNAMI_BASE; 309} 310 311__EXTERN_INLINE int tsunami_is_mmio(const volatile void __iomem *xaddr) 312{ 313 unsigned long addr = (unsigned long) xaddr; 314 return (addr & 0x100000000UL) == 0; 315} 316 317#undef __IO_PREFIX 318#define __IO_PREFIX tsunami 319#define tsunami_trivial_rw_bw 1 320#define tsunami_trivial_rw_lq 1 321#define tsunami_trivial_io_bw 1 322#define tsunami_trivial_io_lq 1 323#define tsunami_trivial_iounmap 1 324#include <asm/io_trivial.h> 325 326#ifdef __IO_EXTERN_INLINE 327#undef __EXTERN_INLINE 328#undef __IO_EXTERN_INLINE 329#endif 330 331#endif /* __KERNEL__ */ 332 333#endif /* __ALPHA_TSUNAMI__H__ */ 334