1/*	$NetBSD: suniv-ccu-f1c100s.h,v 1.1.1.1 2019/05/25 11:29:13 jmcneill Exp $	*/
2
3/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 *
5 * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
6 *
7 */
8
9#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
10#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
11
12#define CLK_CPU			11
13
14#define CLK_BUS_DMA		14
15#define CLK_BUS_MMC0		15
16#define CLK_BUS_MMC1		16
17#define CLK_BUS_DRAM		17
18#define CLK_BUS_SPI0		18
19#define CLK_BUS_SPI1		19
20#define CLK_BUS_OTG		20
21#define CLK_BUS_VE		21
22#define CLK_BUS_LCD		22
23#define CLK_BUS_DEINTERLACE	23
24#define CLK_BUS_CSI		24
25#define CLK_BUS_TVD		25
26#define CLK_BUS_TVE		26
27#define CLK_BUS_DE_BE		27
28#define CLK_BUS_DE_FE		28
29#define CLK_BUS_CODEC		29
30#define CLK_BUS_SPDIF		30
31#define CLK_BUS_IR		31
32#define CLK_BUS_RSB		32
33#define CLK_BUS_I2S0		33
34#define CLK_BUS_I2C0		34
35#define CLK_BUS_I2C1		35
36#define CLK_BUS_I2C2		36
37#define CLK_BUS_PIO		37
38#define CLK_BUS_UART0		38
39#define CLK_BUS_UART1		39
40#define CLK_BUS_UART2		40
41
42#define CLK_MMC0		41
43#define CLK_MMC0_SAMPLE		42
44#define CLK_MMC0_OUTPUT		43
45#define CLK_MMC1		44
46#define CLK_MMC1_SAMPLE		45
47#define CLK_MMC1_OUTPUT		46
48#define CLK_I2S			47
49#define CLK_SPDIF		48
50
51#define CLK_USB_PHY0		49
52
53#define CLK_DRAM_VE		50
54#define CLK_DRAM_CSI		51
55#define CLK_DRAM_DEINTERLACE	52
56#define CLK_DRAM_TVD		53
57#define CLK_DRAM_DE_FE		54
58#define CLK_DRAM_DE_BE		55
59
60#define CLK_DE_BE		56
61#define CLK_DE_FE		57
62#define CLK_TCON		58
63#define CLK_DEINTERLACE		59
64#define CLK_TVE2_CLK		60
65#define CLK_TVE1_CLK		61
66#define CLK_TVD			62
67#define CLK_CSI			63
68#define CLK_VE			64
69#define CLK_CODEC		65
70#define CLK_AVS			66
71
72#endif
73