1/* $NetBSD: sun50i-h6-ccu.h,v 1.1.1.1 2018/04/28 18:25:53 jmcneill Exp $ */ 2 3// SPDX-License-Identifier: (GPL-2.0+ or MIT) 4/* 5 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 6 */ 7 8#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ 9#define _DT_BINDINGS_CLK_SUN50I_H6_H_ 10 11#define CLK_PLL_PERIPH0 3 12 13#define CLK_CPUX 21 14 15#define CLK_APB1 26 16 17#define CLK_DE 29 18#define CLK_BUS_DE 30 19#define CLK_DEINTERLACE 31 20#define CLK_BUS_DEINTERLACE 32 21#define CLK_GPU 33 22#define CLK_BUS_GPU 34 23#define CLK_CE 35 24#define CLK_BUS_CE 36 25#define CLK_VE 37 26#define CLK_BUS_VE 38 27#define CLK_EMCE 39 28#define CLK_BUS_EMCE 40 29#define CLK_VP9 41 30#define CLK_BUS_VP9 42 31#define CLK_BUS_DMA 43 32#define CLK_BUS_MSGBOX 44 33#define CLK_BUS_SPINLOCK 45 34#define CLK_BUS_HSTIMER 46 35#define CLK_AVS 47 36#define CLK_BUS_DBG 48 37#define CLK_BUS_PSI 49 38#define CLK_BUS_PWM 50 39#define CLK_BUS_IOMMU 51 40 41#define CLK_MBUS_DMA 53 42#define CLK_MBUS_VE 54 43#define CLK_MBUS_CE 55 44#define CLK_MBUS_TS 56 45#define CLK_MBUS_NAND 57 46#define CLK_MBUS_CSI 58 47#define CLK_MBUS_DEINTERLACE 59 48 49#define CLK_NAND0 61 50#define CLK_NAND1 62 51#define CLK_BUS_NAND 63 52#define CLK_MMC0 64 53#define CLK_MMC1 65 54#define CLK_MMC2 66 55#define CLK_BUS_MMC0 67 56#define CLK_BUS_MMC1 68 57#define CLK_BUS_MMC2 69 58#define CLK_BUS_UART0 70 59#define CLK_BUS_UART1 71 60#define CLK_BUS_UART2 72 61#define CLK_BUS_UART3 73 62#define CLK_BUS_I2C0 74 63#define CLK_BUS_I2C1 75 64#define CLK_BUS_I2C2 76 65#define CLK_BUS_I2C3 77 66#define CLK_BUS_SCR0 78 67#define CLK_BUS_SCR1 79 68#define CLK_SPI0 80 69#define CLK_SPI1 81 70#define CLK_BUS_SPI0 82 71#define CLK_BUS_SPI1 83 72#define CLK_BUS_EMAC 84 73#define CLK_TS 85 74#define CLK_BUS_TS 86 75#define CLK_IR_TX 87 76#define CLK_BUS_IR_TX 88 77#define CLK_BUS_THS 89 78#define CLK_I2S3 90 79#define CLK_I2S0 91 80#define CLK_I2S1 92 81#define CLK_I2S2 93 82#define CLK_BUS_I2S0 94 83#define CLK_BUS_I2S1 95 84#define CLK_BUS_I2S2 96 85#define CLK_BUS_I2S3 97 86#define CLK_SPDIF 98 87#define CLK_BUS_SPDIF 99 88#define CLK_DMIC 100 89#define CLK_BUS_DMIC 101 90#define CLK_AUDIO_HUB 102 91#define CLK_BUS_AUDIO_HUB 103 92#define CLK_USB_OHCI0 104 93#define CLK_USB_PHY0 105 94#define CLK_USB_PHY1 106 95#define CLK_USB_OHCI3 107 96#define CLK_USB_PHY3 108 97#define CLK_USB_HSIC_12M 109 98#define CLK_USB_HSIC 110 99#define CLK_BUS_OHCI0 111 100#define CLK_BUS_OHCI3 112 101#define CLK_BUS_EHCI0 113 102#define CLK_BUS_XHCI 114 103#define CLK_BUS_EHCI3 115 104#define CLK_BUS_OTG 116 105#define CLK_PCIE_REF_100M 117 106#define CLK_PCIE_REF 118 107#define CLK_PCIE_REF_OUT 119 108#define CLK_PCIE_MAXI 120 109#define CLK_PCIE_AUX 121 110#define CLK_BUS_PCIE 122 111#define CLK_HDMI 123 112#define CLK_HDMI_SLOW 124 113#define CLK_HDMI_CEC 125 114#define CLK_BUS_HDMI 126 115#define CLK_BUS_TCON_TOP 127 116#define CLK_TCON_LCD0 128 117#define CLK_BUS_TCON_LCD0 129 118#define CLK_TCON_TV0 130 119#define CLK_BUS_TCON_TV0 131 120#define CLK_CSI_CCI 132 121#define CLK_CSI_TOP 133 122#define CLK_CSI_MCLK 134 123#define CLK_BUS_CSI 135 124#define CLK_HDCP 136 125#define CLK_BUS_HDCP 137 126 127#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ 128