1/* $NetBSD: sprd,sc9860-clk.h,v 1.1.1.1 2018/04/28 18:25:53 jmcneill Exp $ */ 2 3// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4// 5// Spreadtrum SC9860 platform clocks 6// 7// Copyright (C) 2017, Spreadtrum Communications Inc. 8 9#ifndef _DT_BINDINGS_CLK_SC9860_H_ 10#define _DT_BINDINGS_CLK_SC9860_H_ 11 12#define CLK_FAC_4M 0 13#define CLK_FAC_2M 1 14#define CLK_FAC_1M 2 15#define CLK_FAC_250K 3 16#define CLK_FAC_RPLL0_26M 4 17#define CLK_FAC_RPLL1_26M 5 18#define CLK_FAC_RCO25M 6 19#define CLK_FAC_RCO4M 7 20#define CLK_FAC_RCO2M 8 21#define CLK_FAC_3K2 9 22#define CLK_FAC_1K 10 23#define CLK_MPLL0_GATE 11 24#define CLK_MPLL1_GATE 12 25#define CLK_DPLL0_GATE 13 26#define CLK_DPLL1_GATE 14 27#define CLK_LTEPLL0_GATE 15 28#define CLK_TWPLL_GATE 16 29#define CLK_LTEPLL1_GATE 17 30#define CLK_RPLL0_GATE 18 31#define CLK_RPLL1_GATE 19 32#define CLK_CPPLL_GATE 20 33#define CLK_GPLL_GATE 21 34#define CLK_PMU_GATE_NUM (CLK_GPLL_GATE + 1) 35 36#define CLK_MPLL0 0 37#define CLK_MPLL1 1 38#define CLK_DPLL0 2 39#define CLK_DPLL1 3 40#define CLK_RPLL0 4 41#define CLK_RPLL1 5 42#define CLK_TWPLL 6 43#define CLK_LTEPLL0 7 44#define CLK_LTEPLL1 8 45#define CLK_GPLL 9 46#define CLK_CPPLL 10 47#define CLK_GPLL_42M5 11 48#define CLK_TWPLL_768M 12 49#define CLK_TWPLL_384M 13 50#define CLK_TWPLL_192M 14 51#define CLK_TWPLL_96M 15 52#define CLK_TWPLL_48M 16 53#define CLK_TWPLL_24M 17 54#define CLK_TWPLL_12M 18 55#define CLK_TWPLL_512M 19 56#define CLK_TWPLL_256M 20 57#define CLK_TWPLL_128M 21 58#define CLK_TWPLL_64M 22 59#define CLK_TWPLL_307M2 23 60#define CLK_TWPLL_153M6 24 61#define CLK_TWPLL_76M8 25 62#define CLK_TWPLL_51M2 26 63#define CLK_TWPLL_38M4 27 64#define CLK_TWPLL_19M2 28 65#define CLK_L0_614M4 29 66#define CLK_L0_409M6 30 67#define CLK_L0_38M 31 68#define CLK_L1_38M 32 69#define CLK_RPLL0_192M 33 70#define CLK_RPLL0_96M 34 71#define CLK_RPLL0_48M 35 72#define CLK_RPLL1_468M 36 73#define CLK_RPLL1_192M 37 74#define CLK_RPLL1_96M 38 75#define CLK_RPLL1_64M 39 76#define CLK_RPLL1_48M 40 77#define CLK_DPLL0_50M 41 78#define CLK_DPLL1_50M 42 79#define CLK_CPPLL_50M 43 80#define CLK_M0_39M 44 81#define CLK_M1_63M 45 82#define CLK_PLL_NUM (CLK_M1_63M + 1) 83 84 85#define CLK_AP_APB 0 86#define CLK_AP_USB3 1 87#define CLK_UART0 2 88#define CLK_UART1 3 89#define CLK_UART2 4 90#define CLK_UART3 5 91#define CLK_UART4 6 92#define CLK_I2C0 7 93#define CLK_I2C1 8 94#define CLK_I2C2 9 95#define CLK_I2C3 10 96#define CLK_I2C4 11 97#define CLK_I2C5 12 98#define CLK_SPI0 13 99#define CLK_SPI1 14 100#define CLK_SPI2 15 101#define CLK_SPI3 16 102#define CLK_IIS0 17 103#define CLK_IIS1 18 104#define CLK_IIS2 19 105#define CLK_IIS3 20 106#define CLK_AP_CLK_NUM (CLK_IIS3 + 1) 107 108#define CLK_AON_APB 0 109#define CLK_AUX0 1 110#define CLK_AUX1 2 111#define CLK_AUX2 3 112#define CLK_PROBE 4 113#define CLK_SP_AHB 5 114#define CLK_CCI 6 115#define CLK_GIC 7 116#define CLK_CSSYS 8 117#define CLK_SDIO0_2X 9 118#define CLK_SDIO1_2X 10 119#define CLK_SDIO2_2X 11 120#define CLK_EMMC_2X 12 121#define CLK_SDIO0_1X 13 122#define CLK_SDIO1_1X 14 123#define CLK_SDIO2_1X 15 124#define CLK_EMMC_1X 16 125#define CLK_ADI 17 126#define CLK_PWM0 18 127#define CLK_PWM1 19 128#define CLK_PWM2 20 129#define CLK_PWM3 21 130#define CLK_EFUSE 22 131#define CLK_CM3_UART0 23 132#define CLK_CM3_UART1 24 133#define CLK_THM 25 134#define CLK_CM3_I2C0 26 135#define CLK_CM3_I2C1 27 136#define CLK_CM4_SPI 28 137#define CLK_AON_I2C 29 138#define CLK_AVS 30 139#define CLK_CA53_DAP 31 140#define CLK_CA53_TS 32 141#define CLK_DJTAG_TCK 33 142#define CLK_PMU 34 143#define CLK_PMU_26M 35 144#define CLK_DEBOUNCE 36 145#define CLK_OTG2_REF 37 146#define CLK_USB3_REF 38 147#define CLK_AP_AXI 39 148#define CLK_AON_PREDIV_NUM (CLK_AP_AXI + 1) 149 150#define CLK_USB3_EB 0 151#define CLK_USB3_SUSPEND_EB 1 152#define CLK_USB3_REF_EB 2 153#define CLK_DMA_EB 3 154#define CLK_SDIO0_EB 4 155#define CLK_SDIO1_EB 5 156#define CLK_SDIO2_EB 6 157#define CLK_EMMC_EB 7 158#define CLK_ROM_EB 8 159#define CLK_BUSMON_EB 9 160#define CLK_CC63S_EB 10 161#define CLK_CC63P_EB 11 162#define CLK_CE0_EB 12 163#define CLK_CE1_EB 13 164#define CLK_APAHB_GATE_NUM (CLK_CE1_EB + 1) 165 166#define CLK_AVS_LIT_EB 0 167#define CLK_AVS_BIG_EB 1 168#define CLK_AP_INTC5_EB 2 169#define CLK_GPIO_EB 3 170#define CLK_PWM0_EB 4 171#define CLK_PWM1_EB 5 172#define CLK_PWM2_EB 6 173#define CLK_PWM3_EB 7 174#define CLK_KPD_EB 8 175#define CLK_AON_SYS_EB 9 176#define CLK_AP_SYS_EB 10 177#define CLK_AON_TMR_EB 11 178#define CLK_AP_TMR0_EB 12 179#define CLK_EFUSE_EB 13 180#define CLK_EIC_EB 14 181#define CLK_PUB1_REG_EB 15 182#define CLK_ADI_EB 16 183#define CLK_AP_INTC0_EB 17 184#define CLK_AP_INTC1_EB 18 185#define CLK_AP_INTC2_EB 19 186#define CLK_AP_INTC3_EB 20 187#define CLK_AP_INTC4_EB 21 188#define CLK_SPLK_EB 22 189#define CLK_MSPI_EB 23 190#define CLK_PUB0_REG_EB 24 191#define CLK_PIN_EB 25 192#define CLK_AON_CKG_EB 26 193#define CLK_GPU_EB 27 194#define CLK_APCPU_TS0_EB 28 195#define CLK_APCPU_TS1_EB 29 196#define CLK_DAP_EB 30 197#define CLK_I2C_EB 31 198#define CLK_PMU_EB 32 199#define CLK_THM_EB 33 200#define CLK_AUX0_EB 34 201#define CLK_AUX1_EB 35 202#define CLK_AUX2_EB 36 203#define CLK_PROBE_EB 37 204#define CLK_GPU0_AVS_EB 38 205#define CLK_GPU1_AVS_EB 39 206#define CLK_APCPU_WDG_EB 40 207#define CLK_AP_TMR1_EB 41 208#define CLK_AP_TMR2_EB 42 209#define CLK_DISP_EMC_EB 43 210#define CLK_ZIP_EMC_EB 44 211#define CLK_GSP_EMC_EB 45 212#define CLK_OSC_AON_EB 46 213#define CLK_LVDS_TRX_EB 47 214#define CLK_LVDS_TCXO_EB 48 215#define CLK_MDAR_EB 49 216#define CLK_RTC4M0_CAL_EB 50 217#define CLK_RCT100M_CAL_EB 51 218#define CLK_DJTAG_EB 52 219#define CLK_MBOX_EB 53 220#define CLK_AON_DMA_EB 54 221#define CLK_DBG_EMC_EB 55 222#define CLK_LVDS_PLL_DIV_EN 56 223#define CLK_DEF_EB 57 224#define CLK_AON_APB_RSV0 58 225#define CLK_ORP_JTAG_EB 59 226#define CLK_VSP_EB 60 227#define CLK_CAM_EB 61 228#define CLK_DISP_EB 62 229#define CLK_DBG_AXI_IF_EB 63 230#define CLK_SDIO0_2X_EN 64 231#define CLK_SDIO1_2X_EN 65 232#define CLK_SDIO2_2X_EN 66 233#define CLK_EMMC_2X_EN 67 234#define CLK_ARCH_RTC_EB 68 235#define CLK_KPB_RTC_EB 69 236#define CLK_AON_SYST_RTC_EB 70 237#define CLK_AP_SYST_RTC_EB 71 238#define CLK_AON_TMR_RTC_EB 72 239#define CLK_AP_TMR0_RTC_EB 73 240#define CLK_EIC_RTC_EB 74 241#define CLK_EIC_RTCDV5_EB 75 242#define CLK_AP_WDG_RTC_EB 76 243#define CLK_AP_TMR1_RTC_EB 77 244#define CLK_AP_TMR2_RTC_EB 78 245#define CLK_DCXO_TMR_RTC_EB 79 246#define CLK_BB_CAL_RTC_EB 80 247#define CLK_AVS_BIG_RTC_EB 81 248#define CLK_AVS_LIT_RTC_EB 82 249#define CLK_AVS_GPU0_RTC_EB 83 250#define CLK_AVS_GPU1_RTC_EB 84 251#define CLK_GPU_TS_EB 85 252#define CLK_RTCDV10_EB 86 253#define CLK_AON_GATE_NUM (CLK_RTCDV10_EB + 1) 254 255#define CLK_LIT_MCU 0 256#define CLK_BIG_MCU 1 257#define CLK_AONSECURE_NUM (CLK_BIG_MCU + 1) 258 259#define CLK_AGCP_IIS0_EB 0 260#define CLK_AGCP_IIS1_EB 1 261#define CLK_AGCP_IIS2_EB 2 262#define CLK_AGCP_IIS3_EB 3 263#define CLK_AGCP_UART_EB 4 264#define CLK_AGCP_DMACP_EB 5 265#define CLK_AGCP_DMAAP_EB 6 266#define CLK_AGCP_ARC48K_EB 7 267#define CLK_AGCP_SRC44P1K_EB 8 268#define CLK_AGCP_MCDT_EB 9 269#define CLK_AGCP_VBCIFD_EB 10 270#define CLK_AGCP_VBC_EB 11 271#define CLK_AGCP_SPINLOCK_EB 12 272#define CLK_AGCP_ICU_EB 13 273#define CLK_AGCP_AP_ASHB_EB 14 274#define CLK_AGCP_CP_ASHB_EB 15 275#define CLK_AGCP_AUD_EB 16 276#define CLK_AGCP_AUDIF_EB 17 277#define CLK_AGCP_GATE_NUM (CLK_AGCP_AUDIF_EB + 1) 278 279#define CLK_GPU 0 280#define CLK_GPU_NUM (CLK_GPU + 1) 281 282#define CLK_AHB_VSP 0 283#define CLK_VSP 1 284#define CLK_VSP_ENC 2 285#define CLK_VPP 3 286#define CLK_VSP_26M 4 287#define CLK_VSP_NUM (CLK_VSP_26M + 1) 288 289#define CLK_VSP_DEC_EB 0 290#define CLK_VSP_CKG_EB 1 291#define CLK_VSP_MMU_EB 2 292#define CLK_VSP_ENC_EB 3 293#define CLK_VPP_EB 4 294#define CLK_VSP_26M_EB 5 295#define CLK_VSP_AXI_GATE 6 296#define CLK_VSP_ENC_GATE 7 297#define CLK_VPP_AXI_GATE 8 298#define CLK_VSP_BM_GATE 9 299#define CLK_VSP_ENC_BM_GATE 10 300#define CLK_VPP_BM_GATE 11 301#define CLK_VSP_GATE_NUM (CLK_VPP_BM_GATE + 1) 302 303#define CLK_AHB_CAM 0 304#define CLK_SENSOR0 1 305#define CLK_SENSOR1 2 306#define CLK_SENSOR2 3 307#define CLK_MIPI_CSI0_EB 4 308#define CLK_MIPI_CSI1_EB 5 309#define CLK_CAM_NUM (CLK_MIPI_CSI1_EB + 1) 310 311#define CLK_DCAM0_EB 0 312#define CLK_DCAM1_EB 1 313#define CLK_ISP0_EB 2 314#define CLK_CSI0_EB 3 315#define CLK_CSI1_EB 4 316#define CLK_JPG0_EB 5 317#define CLK_JPG1_EB 6 318#define CLK_CAM_CKG_EB 7 319#define CLK_CAM_MMU_EB 8 320#define CLK_ISP1_EB 9 321#define CLK_CPP_EB 10 322#define CLK_MMU_PF_EB 11 323#define CLK_ISP2_EB 12 324#define CLK_DCAM2ISP_IF_EB 13 325#define CLK_ISP2DCAM_IF_EB 14 326#define CLK_ISP_LCLK_EB 15 327#define CLK_ISP_ICLK_EB 16 328#define CLK_ISP_MCLK_EB 17 329#define CLK_ISP_PCLK_EB 18 330#define CLK_ISP_ISP2DCAM_EB 19 331#define CLK_DCAM0_IF_EB 20 332#define CLK_CLK26M_IF_EB 21 333#define CLK_CPHY0_GATE 22 334#define CLK_MIPI_CSI0_GATE 23 335#define CLK_CPHY1_GATE 24 336#define CLK_MIPI_CSI1 25 337#define CLK_DCAM0_AXI_GATE 26 338#define CLK_DCAM1_AXI_GATE 27 339#define CLK_SENSOR0_GATE 28 340#define CLK_SENSOR1_GATE 29 341#define CLK_JPG0_AXI_GATE 30 342#define CLK_GPG1_AXI_GATE 31 343#define CLK_ISP0_AXI_GATE 32 344#define CLK_ISP1_AXI_GATE 33 345#define CLK_ISP2_AXI_GATE 34 346#define CLK_CPP_AXI_GATE 35 347#define CLK_D0_IF_AXI_GATE 36 348#define CLK_D2I_IF_AXI_GATE 37 349#define CLK_I2D_IF_AXI_GATE 38 350#define CLK_SPARE_AXI_GATE 39 351#define CLK_SENSOR2_GATE 40 352#define CLK_D0IF_IN_D_EN 41 353#define CLK_D1IF_IN_D_EN 42 354#define CLK_D0IF_IN_D2I_EN 43 355#define CLK_D1IF_IN_D2I_EN 44 356#define CLK_IA_IN_D2I_EN 45 357#define CLK_IB_IN_D2I_EN 46 358#define CLK_IC_IN_D2I_EN 47 359#define CLK_IA_IN_I_EN 48 360#define CLK_IB_IN_I_EN 49 361#define CLK_IC_IN_I_EN 50 362#define CLK_CAM_GATE_NUM (CLK_IC_IN_I_EN + 1) 363 364#define CLK_AHB_DISP 0 365#define CLK_DISPC0_DPI 1 366#define CLK_DISPC1_DPI 2 367#define CLK_DISP_NUM (CLK_DISPC1_DPI + 1) 368 369#define CLK_DISPC0_EB 0 370#define CLK_DISPC1_EB 1 371#define CLK_DISPC_MMU_EB 2 372#define CLK_GSP0_EB 3 373#define CLK_GSP1_EB 4 374#define CLK_GSP0_MMU_EB 5 375#define CLK_GSP1_MMU_EB 6 376#define CLK_DSI0_EB 7 377#define CLK_DSI1_EB 8 378#define CLK_DISP_CKG_EB 9 379#define CLK_DISP_GPU_EB 10 380#define CLK_GPU_MTX_EB 11 381#define CLK_GSP_MTX_EB 12 382#define CLK_TMC_MTX_EB 13 383#define CLK_DISPC_MTX_EB 14 384#define CLK_DPHY0_GATE 15 385#define CLK_DPHY1_GATE 16 386#define CLK_GSP0_A_GATE 17 387#define CLK_GSP1_A_GATE 18 388#define CLK_GSP0_F_GATE 19 389#define CLK_GSP1_F_GATE 20 390#define CLK_D_MTX_F_GATE 21 391#define CLK_D_MTX_A_GATE 22 392#define CLK_D_NOC_F_GATE 23 393#define CLK_D_NOC_A_GATE 24 394#define CLK_GSP_MTX_F_GATE 25 395#define CLK_GSP_MTX_A_GATE 26 396#define CLK_GSP_NOC_F_GATE 27 397#define CLK_GSP_NOC_A_GATE 28 398#define CLK_DISPM0IDLE_GATE 29 399#define CLK_GSPM0IDLE_GATE 30 400#define CLK_DISP_GATE_NUM (CLK_GSPM0IDLE_GATE + 1) 401 402#define CLK_SIM0_EB 0 403#define CLK_IIS0_EB 1 404#define CLK_IIS1_EB 2 405#define CLK_IIS2_EB 3 406#define CLK_IIS3_EB 4 407#define CLK_SPI0_EB 5 408#define CLK_SPI1_EB 6 409#define CLK_SPI2_EB 7 410#define CLK_I2C0_EB 8 411#define CLK_I2C1_EB 9 412#define CLK_I2C2_EB 10 413#define CLK_I2C3_EB 11 414#define CLK_I2C4_EB 12 415#define CLK_I2C5_EB 13 416#define CLK_UART0_EB 14 417#define CLK_UART1_EB 15 418#define CLK_UART2_EB 16 419#define CLK_UART3_EB 17 420#define CLK_UART4_EB 18 421#define CLK_AP_CKG_EB 19 422#define CLK_SPI3_EB 20 423#define CLK_APAPB_GATE_NUM (CLK_SPI3_EB + 1) 424 425#endif /* _DT_BINDINGS_CLK_SC9860_H_ */ 426