1/* $NetBSD: samsung,s3c64xx-clock.h,v 1.1.1.2 2019/01/22 14:57:02 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0 */ 4/* 5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com> 6 * 7 * Device Tree binding constants for Samsung S3C64xx clock controller. 8 */ 9 10#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H 11#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H 12 13/* 14 * Let each exported clock get a unique index, which is used on DT-enabled 15 * platforms to lookup the clock from a clock specifier. These indices are 16 * therefore considered an ABI and so must not be changed. This implies 17 * that new clocks should be added either in free spaces between clock groups 18 * or at the end. 19 */ 20 21/* Core clocks. */ 22#define CLK27M 1 23#define CLK48M 2 24#define FOUT_APLL 3 25#define FOUT_MPLL 4 26#define FOUT_EPLL 5 27#define ARMCLK 6 28#define HCLKX2 7 29#define HCLK 8 30#define PCLK 9 31 32/* HCLK bus clocks. */ 33#define HCLK_3DSE 16 34#define HCLK_UHOST 17 35#define HCLK_SECUR 18 36#define HCLK_SDMA1 19 37#define HCLK_SDMA0 20 38#define HCLK_IROM 21 39#define HCLK_DDR1 22 40#define HCLK_MEM1 23 41#define HCLK_MEM0 24 42#define HCLK_USB 25 43#define HCLK_HSMMC2 26 44#define HCLK_HSMMC1 27 45#define HCLK_HSMMC0 28 46#define HCLK_MDP 29 47#define HCLK_DHOST 30 48#define HCLK_IHOST 31 49#define HCLK_DMA1 32 50#define HCLK_DMA0 33 51#define HCLK_JPEG 34 52#define HCLK_CAMIF 35 53#define HCLK_SCALER 36 54#define HCLK_2D 37 55#define HCLK_TV 38 56#define HCLK_POST0 39 57#define HCLK_ROT 40 58#define HCLK_LCD 41 59#define HCLK_TZIC 42 60#define HCLK_INTC 43 61#define HCLK_MFC 44 62#define HCLK_DDR0 45 63 64/* PCLK bus clocks. */ 65#define PCLK_IIC1 48 66#define PCLK_IIS2 49 67#define PCLK_SKEY 50 68#define PCLK_CHIPID 51 69#define PCLK_SPI1 52 70#define PCLK_SPI0 53 71#define PCLK_HSIRX 54 72#define PCLK_HSITX 55 73#define PCLK_GPIO 56 74#define PCLK_IIC0 57 75#define PCLK_IIS1 58 76#define PCLK_IIS0 59 77#define PCLK_AC97 60 78#define PCLK_TZPC 61 79#define PCLK_TSADC 62 80#define PCLK_KEYPAD 63 81#define PCLK_IRDA 64 82#define PCLK_PCM1 65 83#define PCLK_PCM0 66 84#define PCLK_PWM 67 85#define PCLK_RTC 68 86#define PCLK_WDT 69 87#define PCLK_UART3 70 88#define PCLK_UART2 71 89#define PCLK_UART1 72 90#define PCLK_UART0 73 91#define PCLK_MFC 74 92 93/* Special clocks. */ 94#define SCLK_UHOST 80 95#define SCLK_MMC2_48 81 96#define SCLK_MMC1_48 82 97#define SCLK_MMC0_48 83 98#define SCLK_MMC2 84 99#define SCLK_MMC1 85 100#define SCLK_MMC0 86 101#define SCLK_SPI1_48 87 102#define SCLK_SPI0_48 88 103#define SCLK_SPI1 89 104#define SCLK_SPI0 90 105#define SCLK_DAC27 91 106#define SCLK_TV27 92 107#define SCLK_SCALER27 93 108#define SCLK_SCALER 94 109#define SCLK_LCD27 95 110#define SCLK_LCD 96 111#define SCLK_FIMC 97 112#define SCLK_POST0_27 98 113#define SCLK_AUDIO2 99 114#define SCLK_POST0 100 115#define SCLK_AUDIO1 101 116#define SCLK_AUDIO0 102 117#define SCLK_SECUR 103 118#define SCLK_IRDA 104 119#define SCLK_UART 105 120#define SCLK_MFC 106 121#define SCLK_CAM 107 122#define SCLK_JPEG 108 123#define SCLK_ONENAND 109 124 125/* MEM0 bus clocks - S3C6410-specific. */ 126#define MEM0_CFCON 112 127#define MEM0_ONENAND1 113 128#define MEM0_ONENAND0 114 129#define MEM0_NFCON 115 130#define MEM0_SROM 116 131 132/* Muxes. */ 133#define MOUT_APLL 128 134#define MOUT_MPLL 129 135#define MOUT_EPLL 130 136#define MOUT_MFC 131 137#define MOUT_AUDIO0 132 138#define MOUT_AUDIO1 133 139#define MOUT_UART 134 140#define MOUT_SPI0 135 141#define MOUT_SPI1 136 142#define MOUT_MMC0 137 143#define MOUT_MMC1 138 144#define MOUT_MMC2 139 145#define MOUT_UHOST 140 146#define MOUT_IRDA 141 147#define MOUT_LCD 142 148#define MOUT_SCALER 143 149#define MOUT_DAC27 144 150#define MOUT_TV27 145 151#define MOUT_AUDIO2 146 152 153/* Dividers. */ 154#define DOUT_MPLL 160 155#define DOUT_SECUR 161 156#define DOUT_CAM 162 157#define DOUT_JPEG 163 158#define DOUT_MFC 164 159#define DOUT_MMC0 165 160#define DOUT_MMC1 166 161#define DOUT_MMC2 167 162#define DOUT_LCD 168 163#define DOUT_SCALER 169 164#define DOUT_UHOST 170 165#define DOUT_SPI0 171 166#define DOUT_SPI1 172 167#define DOUT_AUDIO0 173 168#define DOUT_AUDIO1 174 169#define DOUT_UART 175 170#define DOUT_IRDA 176 171#define DOUT_FIMC 177 172#define DOUT_AUDIO2 178 173 174/* Total number of clocks. */ 175#define NR_CLKS (DOUT_AUDIO2 + 1) 176 177#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */ 178