1/* $NetBSD: rk3328-cru.h,v 1.1.1.5 2020/01/03 14:33:06 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-or-later */ 4/* 5 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 6 * Author: Elaine <zhangqing@rock-chips.com> 7 */ 8 9#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H 10#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H 11 12/* core clocks */ 13#define PLL_APLL 1 14#define PLL_DPLL 2 15#define PLL_CPLL 3 16#define PLL_GPLL 4 17#define PLL_NPLL 5 18#define ARMCLK 6 19 20/* sclk gates (special clocks) */ 21#define SCLK_RTC32K 30 22#define SCLK_SDMMC_EXT 31 23#define SCLK_SPI 32 24#define SCLK_SDMMC 33 25#define SCLK_SDIO 34 26#define SCLK_EMMC 35 27#define SCLK_TSADC 36 28#define SCLK_SARADC 37 29#define SCLK_UART0 38 30#define SCLK_UART1 39 31#define SCLK_UART2 40 32#define SCLK_I2S0 41 33#define SCLK_I2S1 42 34#define SCLK_I2S2 43 35#define SCLK_I2S1_OUT 44 36#define SCLK_I2S2_OUT 45 37#define SCLK_SPDIF 46 38#define SCLK_TIMER0 47 39#define SCLK_TIMER1 48 40#define SCLK_TIMER2 49 41#define SCLK_TIMER3 50 42#define SCLK_TIMER4 51 43#define SCLK_TIMER5 52 44#define SCLK_WIFI 53 45#define SCLK_CIF_OUT 54 46#define SCLK_I2C0 55 47#define SCLK_I2C1 56 48#define SCLK_I2C2 57 49#define SCLK_I2C3 58 50#define SCLK_CRYPTO 59 51#define SCLK_PWM 60 52#define SCLK_PDM 61 53#define SCLK_EFUSE 62 54#define SCLK_OTP 63 55#define SCLK_DDRCLK 64 56#define SCLK_VDEC_CABAC 65 57#define SCLK_VDEC_CORE 66 58#define SCLK_VENC_DSP 67 59#define SCLK_VENC_CORE 68 60#define SCLK_RGA 69 61#define SCLK_HDMI_SFC 70 62#define SCLK_HDMI_CEC 71 63#define SCLK_USB3_REF 72 64#define SCLK_USB3_SUSPEND 73 65#define SCLK_SDMMC_DRV 74 66#define SCLK_SDIO_DRV 75 67#define SCLK_EMMC_DRV 76 68#define SCLK_SDMMC_EXT_DRV 77 69#define SCLK_SDMMC_SAMPLE 78 70#define SCLK_SDIO_SAMPLE 79 71#define SCLK_EMMC_SAMPLE 80 72#define SCLK_SDMMC_EXT_SAMPLE 81 73#define SCLK_VOP 82 74#define SCLK_MAC2PHY_RXTX 83 75#define SCLK_MAC2PHY_SRC 84 76#define SCLK_MAC2PHY_REF 85 77#define SCLK_MAC2PHY_OUT 86 78#define SCLK_MAC2IO_RX 87 79#define SCLK_MAC2IO_TX 88 80#define SCLK_MAC2IO_REFOUT 89 81#define SCLK_MAC2IO_REF 90 82#define SCLK_MAC2IO_OUT 91 83#define SCLK_TSP 92 84#define SCLK_HSADC_TSP 93 85#define SCLK_USB3PHY_REF 94 86#define SCLK_REF_USB3OTG 95 87#define SCLK_USB3OTG_REF 96 88#define SCLK_USB3OTG_SUSPEND 97 89#define SCLK_REF_USB3OTG_SRC 98 90#define SCLK_MAC2IO_SRC 99 91#define SCLK_MAC2IO 100 92#define SCLK_MAC2PHY 101 93#define SCLK_MAC2IO_EXT 102 94 95/* dclk gates */ 96#define DCLK_LCDC 120 97#define DCLK_HDMIPHY 121 98#define HDMIPHY 122 99#define USB480M 123 100#define DCLK_LCDC_SRC 124 101 102/* aclk gates */ 103#define ACLK_AXISRAM 130 104#define ACLK_VOP_PRE 131 105#define ACLK_USB3OTG 132 106#define ACLK_RGA_PRE 133 107#define ACLK_DMAC 134 108#define ACLK_GPU 135 109#define ACLK_BUS_PRE 136 110#define ACLK_PERI_PRE 137 111#define ACLK_RKVDEC_PRE 138 112#define ACLK_RKVDEC 139 113#define ACLK_RKVENC 140 114#define ACLK_VPU_PRE 141 115#define ACLK_VIO_PRE 142 116#define ACLK_VPU 143 117#define ACLK_VIO 144 118#define ACLK_VOP 145 119#define ACLK_GMAC 146 120#define ACLK_H265 147 121#define ACLK_H264 148 122#define ACLK_MAC2PHY 149 123#define ACLK_MAC2IO 150 124#define ACLK_DCF 151 125#define ACLK_TSP 152 126#define ACLK_PERI 153 127#define ACLK_RGA 154 128#define ACLK_IEP 155 129#define ACLK_CIF 156 130#define ACLK_HDCP 157 131 132/* pclk gates */ 133#define PCLK_GPIO0 200 134#define PCLK_GPIO1 201 135#define PCLK_GPIO2 202 136#define PCLK_GPIO3 203 137#define PCLK_GRF 204 138#define PCLK_I2C0 205 139#define PCLK_I2C1 206 140#define PCLK_I2C2 207 141#define PCLK_I2C3 208 142#define PCLK_SPI 209 143#define PCLK_UART0 210 144#define PCLK_UART1 211 145#define PCLK_UART2 212 146#define PCLK_TSADC 213 147#define PCLK_PWM 214 148#define PCLK_TIMER 215 149#define PCLK_BUS_PRE 216 150#define PCLK_PERI_PRE 217 151#define PCLK_HDMI_CTRL 218 152#define PCLK_HDMI_PHY 219 153#define PCLK_GMAC 220 154#define PCLK_H265 221 155#define PCLK_MAC2PHY 222 156#define PCLK_MAC2IO 223 157#define PCLK_USB3PHY_OTG 224 158#define PCLK_USB3PHY_PIPE 225 159#define PCLK_USB3_GRF 226 160#define PCLK_USB2_GRF 227 161#define PCLK_HDMIPHY 228 162#define PCLK_DDR 229 163#define PCLK_PERI 230 164#define PCLK_HDMI 231 165#define PCLK_HDCP 232 166#define PCLK_DCF 233 167#define PCLK_SARADC 234 168#define PCLK_ACODECPHY 235 169#define PCLK_WDT 236 170 171/* hclk gates */ 172#define HCLK_PERI 308 173#define HCLK_TSP 309 174#define HCLK_GMAC 310 175#define HCLK_I2S0_8CH 311 176#define HCLK_I2S1_8CH 312 177#define HCLK_I2S2_2CH 313 178#define HCLK_SPDIF_8CH 314 179#define HCLK_VOP 315 180#define HCLK_NANDC 316 181#define HCLK_SDMMC 317 182#define HCLK_SDIO 318 183#define HCLK_EMMC 319 184#define HCLK_SDMMC_EXT 320 185#define HCLK_RKVDEC_PRE 321 186#define HCLK_RKVDEC 322 187#define HCLK_RKVENC 323 188#define HCLK_VPU_PRE 324 189#define HCLK_VIO_PRE 325 190#define HCLK_VPU 326 191#define HCLK_BUS_PRE 328 192#define HCLK_PERI_PRE 329 193#define HCLK_H264 330 194#define HCLK_CIF 331 195#define HCLK_OTG_PMU 332 196#define HCLK_OTG 333 197#define HCLK_HOST0 334 198#define HCLK_HOST0_ARB 335 199#define HCLK_CRYPTO_MST 336 200#define HCLK_CRYPTO_SLV 337 201#define HCLK_PDM 338 202#define HCLK_IEP 339 203#define HCLK_RGA 340 204#define HCLK_HDCP 341 205 206#define CLK_NR_CLKS (HCLK_HDCP + 1) 207 208/* soft-reset indices */ 209#define SRST_CORE0_PO 0 210#define SRST_CORE1_PO 1 211#define SRST_CORE2_PO 2 212#define SRST_CORE3_PO 3 213#define SRST_CORE0 4 214#define SRST_CORE1 5 215#define SRST_CORE2 6 216#define SRST_CORE3 7 217#define SRST_CORE0_DBG 8 218#define SRST_CORE1_DBG 9 219#define SRST_CORE2_DBG 10 220#define SRST_CORE3_DBG 11 221#define SRST_TOPDBG 12 222#define SRST_CORE_NIU 13 223#define SRST_STRC_A 14 224#define SRST_L2C 15 225 226#define SRST_A53_GIC 18 227#define SRST_DAP 19 228#define SRST_PMU_P 21 229#define SRST_EFUSE 22 230#define SRST_BUSSYS_H 23 231#define SRST_BUSSYS_P 24 232#define SRST_SPDIF 25 233#define SRST_INTMEM 26 234#define SRST_ROM 27 235#define SRST_GPIO0 28 236#define SRST_GPIO1 29 237#define SRST_GPIO2 30 238#define SRST_GPIO3 31 239 240#define SRST_I2S0 32 241#define SRST_I2S1 33 242#define SRST_I2S2 34 243#define SRST_I2S0_H 35 244#define SRST_I2S1_H 36 245#define SRST_I2S2_H 37 246#define SRST_UART0 38 247#define SRST_UART1 39 248#define SRST_UART2 40 249#define SRST_UART0_P 41 250#define SRST_UART1_P 42 251#define SRST_UART2_P 43 252#define SRST_I2C0 44 253#define SRST_I2C1 45 254#define SRST_I2C2 46 255#define SRST_I2C3 47 256 257#define SRST_I2C0_P 48 258#define SRST_I2C1_P 49 259#define SRST_I2C2_P 50 260#define SRST_I2C3_P 51 261#define SRST_EFUSE_SE_P 52 262#define SRST_EFUSE_NS_P 53 263#define SRST_PWM0 54 264#define SRST_PWM0_P 55 265#define SRST_DMA 56 266#define SRST_TSP_A 57 267#define SRST_TSP_H 58 268#define SRST_TSP 59 269#define SRST_TSP_HSADC 60 270#define SRST_DCF_A 61 271#define SRST_DCF_P 62 272 273#define SRST_SCR 64 274#define SRST_SPI 65 275#define SRST_TSADC 66 276#define SRST_TSADC_P 67 277#define SRST_CRYPTO 68 278#define SRST_SGRF 69 279#define SRST_GRF 70 280#define SRST_USB_GRF 71 281#define SRST_TIMER_6CH_P 72 282#define SRST_TIMER0 73 283#define SRST_TIMER1 74 284#define SRST_TIMER2 75 285#define SRST_TIMER3 76 286#define SRST_TIMER4 77 287#define SRST_TIMER5 78 288#define SRST_USB3GRF 79 289 290#define SRST_PHYNIU 80 291#define SRST_HDMIPHY 81 292#define SRST_VDAC 82 293#define SRST_ACODEC_p 83 294#define SRST_SARADC 85 295#define SRST_SARADC_P 86 296#define SRST_GRF_DDR 87 297#define SRST_DFIMON 88 298#define SRST_MSCH 89 299#define SRST_DDRMSCH 91 300#define SRST_DDRCTRL 92 301#define SRST_DDRCTRL_P 93 302#define SRST_DDRPHY 94 303#define SRST_DDRPHY_P 95 304 305#define SRST_GMAC_NIU_A 96 306#define SRST_GMAC_NIU_P 97 307#define SRST_GMAC2PHY_A 98 308#define SRST_GMAC2IO_A 99 309#define SRST_MACPHY 100 310#define SRST_OTP_PHY 101 311#define SRST_GPU_A 102 312#define SRST_GPU_NIU_A 103 313#define SRST_SDMMCEXT 104 314#define SRST_PERIPH_NIU_A 105 315#define SRST_PERIHP_NIU_H 106 316#define SRST_PERIHP_P 107 317#define SRST_PERIPHSYS_H 108 318#define SRST_MMC0 109 319#define SRST_SDIO 110 320#define SRST_EMMC 111 321 322#define SRST_USB2OTG_H 112 323#define SRST_USB2OTG 113 324#define SRST_USB2OTG_ADP 114 325#define SRST_USB2HOST_H 115 326#define SRST_USB2HOST_ARB 116 327#define SRST_USB2HOST_AUX 117 328#define SRST_USB2HOST_EHCIPHY 118 329#define SRST_USB2HOST_UTMI 119 330#define SRST_USB3OTG 120 331#define SRST_USBPOR 121 332#define SRST_USB2OTG_UTMI 122 333#define SRST_USB2HOST_PHY_UTMI 123 334#define SRST_USB3OTG_UTMI 124 335#define SRST_USB3PHY_U2 125 336#define SRST_USB3PHY_U3 126 337#define SRST_USB3PHY_PIPE 127 338 339#define SRST_VIO_A 128 340#define SRST_VIO_BUS_H 129 341#define SRST_VIO_H2P_H 130 342#define SRST_VIO_ARBI_H 131 343#define SRST_VOP_NIU_A 132 344#define SRST_VOP_A 133 345#define SRST_VOP_H 134 346#define SRST_VOP_D 135 347#define SRST_RGA 136 348#define SRST_RGA_NIU_A 137 349#define SRST_RGA_A 138 350#define SRST_RGA_H 139 351#define SRST_IEP_A 140 352#define SRST_IEP_H 141 353#define SRST_HDMI 142 354#define SRST_HDMI_P 143 355 356#define SRST_HDCP_A 144 357#define SRST_HDCP 145 358#define SRST_HDCP_H 146 359#define SRST_CIF_A 147 360#define SRST_CIF_H 148 361#define SRST_CIF_P 149 362#define SRST_OTP_P 150 363#define SRST_OTP_SBPI 151 364#define SRST_OTP_USER 152 365#define SRST_DDRCTRL_A 153 366#define SRST_DDRSTDY_P 154 367#define SRST_DDRSTDY 155 368#define SRST_PDM_H 156 369#define SRST_PDM 157 370#define SRST_USB3PHY_OTG_P 158 371#define SRST_USB3PHY_PIPE_P 159 372 373#define SRST_VCODEC_A 160 374#define SRST_VCODEC_NIU_A 161 375#define SRST_VCODEC_H 162 376#define SRST_VCODEC_NIU_H 163 377#define SRST_VDEC_A 164 378#define SRST_VDEC_NIU_A 165 379#define SRST_VDEC_H 166 380#define SRST_VDEC_NIU_H 167 381#define SRST_VDEC_CORE 168 382#define SRST_VDEC_CABAC 169 383#define SRST_DDRPHYDIV 175 384 385#define SRST_RKVENC_NIU_A 176 386#define SRST_RKVENC_NIU_H 177 387#define SRST_RKVENC_H265_A 178 388#define SRST_RKVENC_H265_P 179 389#define SRST_RKVENC_H265_CORE 180 390#define SRST_RKVENC_H265_DSP 181 391#define SRST_RKVENC_H264_A 182 392#define SRST_RKVENC_H264_H 183 393#define SRST_RKVENC_INTMEM 184 394 395#endif 396