1/* $NetBSD: rk3036-cru.h,v 1.1.1.3 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-or-later */ 4/* 5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 6 * Author: Xing Zheng <zhengxing@rock-chips.com> 7 */ 8 9#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H 10#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H 11 12/* core clocks */ 13#define PLL_APLL 1 14#define PLL_DPLL 2 15#define PLL_GPLL 3 16#define ARMCLK 4 17 18/* sclk gates (special clocks) */ 19#define SCLK_GPU 64 20#define SCLK_SPI 65 21#define SCLK_SDMMC 68 22#define SCLK_SDIO 69 23#define SCLK_EMMC 71 24#define SCLK_NANDC 76 25#define SCLK_UART0 77 26#define SCLK_UART1 78 27#define SCLK_UART2 79 28#define SCLK_I2S 82 29#define SCLK_SPDIF 83 30#define SCLK_TIMER0 85 31#define SCLK_TIMER1 86 32#define SCLK_TIMER2 87 33#define SCLK_TIMER3 88 34#define SCLK_OTGPHY0 93 35#define SCLK_LCDC 100 36#define SCLK_HDMI 109 37#define SCLK_HEVC 111 38#define SCLK_I2S_OUT 113 39#define SCLK_SDMMC_DRV 114 40#define SCLK_SDIO_DRV 115 41#define SCLK_EMMC_DRV 117 42#define SCLK_SDMMC_SAMPLE 118 43#define SCLK_SDIO_SAMPLE 119 44#define SCLK_EMMC_SAMPLE 121 45#define SCLK_PVTM_CORE 123 46#define SCLK_PVTM_GPU 124 47#define SCLK_PVTM_VIDEO 125 48#define SCLK_MAC 151 49#define SCLK_MACREF 152 50#define SCLK_MACPLL 153 51#define SCLK_SFC 160 52 53/* aclk gates */ 54#define ACLK_DMAC2 194 55#define ACLK_LCDC 197 56#define ACLK_VIO 203 57#define ACLK_VCODEC 208 58#define ACLK_CPU 209 59#define ACLK_PERI 210 60 61/* pclk gates */ 62#define PCLK_GPIO0 320 63#define PCLK_GPIO1 321 64#define PCLK_GPIO2 322 65#define PCLK_GRF 329 66#define PCLK_I2C0 332 67#define PCLK_I2C1 333 68#define PCLK_I2C2 334 69#define PCLK_SPI 338 70#define PCLK_UART0 341 71#define PCLK_UART1 342 72#define PCLK_UART2 343 73#define PCLK_PWM 350 74#define PCLK_TIMER 353 75#define PCLK_HDMI 360 76#define PCLK_CPU 362 77#define PCLK_PERI 363 78#define PCLK_DDRUPCTL 364 79#define PCLK_WDT 368 80#define PCLK_ACODEC 369 81 82/* hclk gates */ 83#define HCLK_OTG0 449 84#define HCLK_OTG1 450 85#define HCLK_NANDC 453 86#define HCLK_SFC 454 87#define HCLK_SDMMC 456 88#define HCLK_SDIO 457 89#define HCLK_EMMC 459 90#define HCLK_MAC 460 91#define HCLK_I2S 462 92#define HCLK_LCDC 465 93#define HCLK_ROM 467 94#define HCLK_VIO_BUS 472 95#define HCLK_VCODEC 476 96#define HCLK_CPU 477 97#define HCLK_PERI 478 98 99#define CLK_NR_CLKS (HCLK_PERI + 1) 100 101/* soft-reset indices */ 102#define SRST_CORE0 0 103#define SRST_CORE1 1 104#define SRST_CORE0_DBG 4 105#define SRST_CORE1_DBG 5 106#define SRST_CORE0_POR 8 107#define SRST_CORE1_POR 9 108#define SRST_L2C 12 109#define SRST_TOPDBG 13 110#define SRST_STRC_SYS_A 14 111#define SRST_PD_CORE_NIU 15 112 113#define SRST_TIMER2 16 114#define SRST_CPUSYS_H 17 115#define SRST_AHB2APB_H 19 116#define SRST_TIMER3 20 117#define SRST_INTMEM 21 118#define SRST_ROM 22 119#define SRST_PERI_NIU 23 120#define SRST_I2S 24 121#define SRST_DDR_PLL 25 122#define SRST_GPU_DLL 26 123#define SRST_TIMER0 27 124#define SRST_TIMER1 28 125#define SRST_CORE_DLL 29 126#define SRST_EFUSE_P 30 127#define SRST_ACODEC_P 31 128 129#define SRST_GPIO0 32 130#define SRST_GPIO1 33 131#define SRST_GPIO2 34 132#define SRST_UART0 39 133#define SRST_UART1 40 134#define SRST_UART2 41 135#define SRST_I2C0 43 136#define SRST_I2C1 44 137#define SRST_I2C2 45 138#define SRST_SFC 47 139 140#define SRST_PWM0 48 141#define SRST_DAP 51 142#define SRST_DAP_SYS 52 143#define SRST_GRF 55 144#define SRST_PERIPHSYS_A 57 145#define SRST_PERIPHSYS_H 58 146#define SRST_PERIPHSYS_P 59 147#define SRST_CPU_PERI 61 148#define SRST_EMEM_PERI 62 149#define SRST_USB_PERI 63 150 151#define SRST_DMA2 64 152#define SRST_MAC 66 153#define SRST_NANDC 68 154#define SRST_USBOTG0 69 155#define SRST_OTGC0 71 156#define SRST_USBOTG1 72 157#define SRST_OTGC1 74 158#define SRST_DDRMSCH 79 159 160#define SRST_MMC0 81 161#define SRST_SDIO 82 162#define SRST_EMMC 83 163#define SRST_SPI0 84 164#define SRST_WDT 86 165#define SRST_DDRPHY 88 166#define SRST_DDRPHY_P 89 167#define SRST_DDRCTRL 90 168#define SRST_DDRCTRL_P 91 169 170#define SRST_HDMI_P 96 171#define SRST_VIO_BUS_H 99 172#define SRST_UTMI0 103 173#define SRST_UTMI1 104 174#define SRST_USBPOR 105 175 176#define SRST_VCODEC_A 112 177#define SRST_VCODEC_H 113 178#define SRST_VIO1_A 114 179#define SRST_HEVC 115 180#define SRST_VCODEC_NIU_A 116 181#define SRST_LCDC1_A 117 182#define SRST_LCDC1_H 118 183#define SRST_LCDC1_D 119 184#define SRST_GPU 120 185#define SRST_GPU_NIU_A 122 186 187#define SRST_DBG_P 131 188 189#endif 190