1/*	$NetBSD: r9a06g032-sysctrl.h,v 1.1.1.1 2019/01/22 14:57:01 jmcneill Exp $	*/
2
3/* SPDX-License-Identifier: GPL-2.0 */
4/*
5 * R9A06G032 sysctrl IDs
6 *
7 * Copyright (C) 2018 Renesas Electronics Europe Limited
8 *
9 * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
10 */
11
12#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__
13#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__
14
15#define R9A06G032_CLK_PLL_USB		1
16#define R9A06G032_CLK_48		1	/* AKA CLK_PLL_USB */
17#define R9A06G032_MSEBIS_CLK		3	/* AKA CLKOUT_D16 */
18#define R9A06G032_MSEBIM_CLK		3	/* AKA CLKOUT_D16 */
19#define R9A06G032_CLK_DDRPHY_PLLCLK	5	/* AKA CLKOUT_D1OR2 */
20#define R9A06G032_CLK50			6	/* AKA CLKOUT_D20 */
21#define R9A06G032_CLK25			7	/* AKA CLKOUT_D40 */
22#define R9A06G032_CLK125		9	/* AKA CLKOUT_D8 */
23#define R9A06G032_CLK_P5_PG1		17	/* AKA DIV_P5_PG */
24#define R9A06G032_CLK_REF_SYNC		21	/* AKA DIV_REF_SYNC */
25#define R9A06G032_CLK_25_PG4		26
26#define R9A06G032_CLK_25_PG5		27
27#define R9A06G032_CLK_25_PG6		28
28#define R9A06G032_CLK_25_PG7		29
29#define R9A06G032_CLK_25_PG8		30
30#define R9A06G032_CLK_ADC		31
31#define R9A06G032_CLK_ECAT100		32
32#define R9A06G032_CLK_HSR100		33
33#define R9A06G032_CLK_I2C0		34
34#define R9A06G032_CLK_I2C1		35
35#define R9A06G032_CLK_MII_REF		36
36#define R9A06G032_CLK_NAND		37
37#define R9A06G032_CLK_NOUSBP2_PG6	38
38#define R9A06G032_CLK_P1_PG2		39
39#define R9A06G032_CLK_P1_PG3		40
40#define R9A06G032_CLK_P1_PG4		41
41#define R9A06G032_CLK_P4_PG3		42
42#define R9A06G032_CLK_P4_PG4		43
43#define R9A06G032_CLK_P6_PG1		44
44#define R9A06G032_CLK_P6_PG2		45
45#define R9A06G032_CLK_P6_PG3		46
46#define R9A06G032_CLK_P6_PG4		47
47#define R9A06G032_CLK_PCI_USB		48
48#define R9A06G032_CLK_QSPI0		49
49#define R9A06G032_CLK_QSPI1		50
50#define R9A06G032_CLK_RGMII_REF		51
51#define R9A06G032_CLK_RMII_REF		52
52#define R9A06G032_CLK_SDIO0		53
53#define R9A06G032_CLK_SDIO1		54
54#define R9A06G032_CLK_SERCOS100		55
55#define R9A06G032_CLK_SLCD		56
56#define R9A06G032_CLK_SPI0		57
57#define R9A06G032_CLK_SPI1		58
58#define R9A06G032_CLK_SPI2		59
59#define R9A06G032_CLK_SPI3		60
60#define R9A06G032_CLK_SPI4		61
61#define R9A06G032_CLK_SPI5		62
62#define R9A06G032_CLK_SWITCH		63
63#define R9A06G032_HCLK_ECAT125		65
64#define R9A06G032_HCLK_PINCONFIG	66
65#define R9A06G032_HCLK_SERCOS		67
66#define R9A06G032_HCLK_SGPIO2		68
67#define R9A06G032_HCLK_SGPIO3		69
68#define R9A06G032_HCLK_SGPIO4		70
69#define R9A06G032_HCLK_TIMER0		71
70#define R9A06G032_HCLK_TIMER1		72
71#define R9A06G032_HCLK_USBF		73
72#define R9A06G032_HCLK_USBH		74
73#define R9A06G032_HCLK_USBPM		75
74#define R9A06G032_CLK_48_PG_F		76
75#define R9A06G032_CLK_48_PG4		77
76#define R9A06G032_CLK_DDRPHY_PCLK	81	/* AKA CLK_REF_SYNC_D4 */
77#define R9A06G032_CLK_FW		81	/* AKA CLK_REF_SYNC_D4 */
78#define R9A06G032_CLK_CRYPTO		81	/* AKA CLK_REF_SYNC_D4 */
79#define R9A06G032_CLK_A7MP		84	/* AKA DIV_CA7 */
80#define R9A06G032_HCLK_CAN0		85
81#define R9A06G032_HCLK_CAN1		86
82#define R9A06G032_HCLK_DELTASIGMA	87
83#define R9A06G032_HCLK_PWMPTO		88
84#define R9A06G032_HCLK_RSV		89
85#define R9A06G032_HCLK_SGPIO0		90
86#define R9A06G032_HCLK_SGPIO1		91
87#define R9A06G032_RTOS_MDC		92
88#define R9A06G032_CLK_CM3		93
89#define R9A06G032_CLK_DDRC		94
90#define R9A06G032_CLK_ECAT25		95
91#define R9A06G032_CLK_HSR50		96
92#define R9A06G032_CLK_HW_RTOS		97
93#define R9A06G032_CLK_SERCOS50		98
94#define R9A06G032_HCLK_ADC		99
95#define R9A06G032_HCLK_CM3		100
96#define R9A06G032_HCLK_CRYPTO_EIP150	101
97#define R9A06G032_HCLK_CRYPTO_EIP93	102
98#define R9A06G032_HCLK_DDRC		103
99#define R9A06G032_HCLK_DMA0		104
100#define R9A06G032_HCLK_DMA1		105
101#define R9A06G032_HCLK_GMAC0		106
102#define R9A06G032_HCLK_GMAC1		107
103#define R9A06G032_HCLK_GPIO0		108
104#define R9A06G032_HCLK_GPIO1		109
105#define R9A06G032_HCLK_GPIO2		110
106#define R9A06G032_HCLK_HSR		111
107#define R9A06G032_HCLK_I2C0		112
108#define R9A06G032_HCLK_I2C1		113
109#define R9A06G032_HCLK_LCD		114
110#define R9A06G032_HCLK_MSEBI_M		115
111#define R9A06G032_HCLK_MSEBI_S		116
112#define R9A06G032_HCLK_NAND		117
113#define R9A06G032_HCLK_PG_I		118
114#define R9A06G032_HCLK_PG19		119
115#define R9A06G032_HCLK_PG20		120
116#define R9A06G032_HCLK_PG3		121
117#define R9A06G032_HCLK_PG4		122
118#define R9A06G032_HCLK_QSPI0		123
119#define R9A06G032_HCLK_QSPI1		124
120#define R9A06G032_HCLK_ROM		125
121#define R9A06G032_HCLK_RTC		126
122#define R9A06G032_HCLK_SDIO0		127
123#define R9A06G032_HCLK_SDIO1		128
124#define R9A06G032_HCLK_SEMAP		129
125#define R9A06G032_HCLK_SPI0		130
126#define R9A06G032_HCLK_SPI1		131
127#define R9A06G032_HCLK_SPI2		132
128#define R9A06G032_HCLK_SPI3		133
129#define R9A06G032_HCLK_SPI4		134
130#define R9A06G032_HCLK_SPI5		135
131#define R9A06G032_HCLK_SWITCH		136
132#define R9A06G032_HCLK_SWITCH_RG	137
133#define R9A06G032_HCLK_UART0		138
134#define R9A06G032_HCLK_UART1		139
135#define R9A06G032_HCLK_UART2		140
136#define R9A06G032_HCLK_UART3		141
137#define R9A06G032_HCLK_UART4		142
138#define R9A06G032_HCLK_UART5		143
139#define R9A06G032_HCLK_UART6		144
140#define R9A06G032_HCLK_UART7		145
141#define R9A06G032_CLK_UART0		146
142#define R9A06G032_CLK_UART1		147
143#define R9A06G032_CLK_UART2		148
144#define R9A06G032_CLK_UART3		149
145#define R9A06G032_CLK_UART4		150
146#define R9A06G032_CLK_UART5		151
147#define R9A06G032_CLK_UART6		152
148#define R9A06G032_CLK_UART7		153
149
150#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */
151