1/* $NetBSD: r8a7794-clock.h,v 1.1.1.3 2019/01/22 14:57:02 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0+ 4 * 5 * Copyright (C) 2014 Renesas Electronics Corporation 6 * Copyright 2013 Ideas On Board SPRL 7 */ 8 9#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ 10#define __DT_BINDINGS_CLOCK_R8A7794_H__ 11 12/* CPG */ 13#define R8A7794_CLK_MAIN 0 14#define R8A7794_CLK_PLL0 1 15#define R8A7794_CLK_PLL1 2 16#define R8A7794_CLK_PLL3 3 17#define R8A7794_CLK_LB 4 18#define R8A7794_CLK_QSPI 5 19#define R8A7794_CLK_SDH 6 20#define R8A7794_CLK_SD0 7 21#define R8A7794_CLK_RCAN 8 22 23/* MSTP0 */ 24#define R8A7794_CLK_MSIOF0 0 25 26/* MSTP1 */ 27#define R8A7794_CLK_VCP0 1 28#define R8A7794_CLK_VPC0 3 29#define R8A7794_CLK_TMU1 11 30#define R8A7794_CLK_3DG 12 31#define R8A7794_CLK_2DDMAC 15 32#define R8A7794_CLK_FDP1_0 19 33#define R8A7794_CLK_TMU3 21 34#define R8A7794_CLK_TMU2 22 35#define R8A7794_CLK_CMT0 24 36#define R8A7794_CLK_TMU0 25 37#define R8A7794_CLK_VSP1_DU0 28 38#define R8A7794_CLK_VSP1_S 31 39 40/* MSTP2 */ 41#define R8A7794_CLK_SCIFA2 2 42#define R8A7794_CLK_SCIFA1 3 43#define R8A7794_CLK_SCIFA0 4 44#define R8A7794_CLK_MSIOF2 5 45#define R8A7794_CLK_SCIFB0 6 46#define R8A7794_CLK_SCIFB1 7 47#define R8A7794_CLK_MSIOF1 8 48#define R8A7794_CLK_SCIFB2 16 49#define R8A7794_CLK_SYS_DMAC1 18 50#define R8A7794_CLK_SYS_DMAC0 19 51 52/* MSTP3 */ 53#define R8A7794_CLK_SDHI2 11 54#define R8A7794_CLK_SDHI1 12 55#define R8A7794_CLK_SDHI0 14 56#define R8A7794_CLK_MMCIF0 15 57#define R8A7794_CLK_IIC0 18 58#define R8A7794_CLK_IIC1 23 59#define R8A7794_CLK_CMT1 29 60#define R8A7794_CLK_USBDMAC0 30 61#define R8A7794_CLK_USBDMAC1 31 62 63/* MSTP4 */ 64#define R8A7794_CLK_IRQC 7 65#define R8A7794_CLK_INTC_SYS 8 66 67/* MSTP5 */ 68#define R8A7794_CLK_AUDIO_DMAC0 2 69#define R8A7794_CLK_PWM 23 70 71/* MSTP7 */ 72#define R8A7794_CLK_EHCI 3 73#define R8A7794_CLK_HSUSB 4 74#define R8A7794_CLK_HSCIF2 13 75#define R8A7794_CLK_SCIF5 14 76#define R8A7794_CLK_SCIF4 15 77#define R8A7794_CLK_HSCIF1 16 78#define R8A7794_CLK_HSCIF0 17 79#define R8A7794_CLK_SCIF3 18 80#define R8A7794_CLK_SCIF2 19 81#define R8A7794_CLK_SCIF1 20 82#define R8A7794_CLK_SCIF0 21 83#define R8A7794_CLK_DU1 23 84#define R8A7794_CLK_DU0 24 85 86/* MSTP8 */ 87#define R8A7794_CLK_VIN1 10 88#define R8A7794_CLK_VIN0 11 89#define R8A7794_CLK_ETHERAVB 12 90#define R8A7794_CLK_ETHER 13 91 92/* MSTP9 */ 93#define R8A7794_CLK_GPIO6 5 94#define R8A7794_CLK_GPIO5 7 95#define R8A7794_CLK_GPIO4 8 96#define R8A7794_CLK_GPIO3 9 97#define R8A7794_CLK_GPIO2 10 98#define R8A7794_CLK_GPIO1 11 99#define R8A7794_CLK_GPIO0 12 100#define R8A7794_CLK_RCAN1 15 101#define R8A7794_CLK_RCAN0 16 102#define R8A7794_CLK_QSPI_MOD 17 103#define R8A7794_CLK_I2C5 25 104#define R8A7794_CLK_I2C4 27 105#define R8A7794_CLK_I2C3 28 106#define R8A7794_CLK_I2C2 29 107#define R8A7794_CLK_I2C1 30 108#define R8A7794_CLK_I2C0 31 109 110/* MSTP10 */ 111#define R8A7794_CLK_SSI_ALL 5 112#define R8A7794_CLK_SSI9 6 113#define R8A7794_CLK_SSI8 7 114#define R8A7794_CLK_SSI7 8 115#define R8A7794_CLK_SSI6 9 116#define R8A7794_CLK_SSI5 10 117#define R8A7794_CLK_SSI4 11 118#define R8A7794_CLK_SSI3 12 119#define R8A7794_CLK_SSI2 13 120#define R8A7794_CLK_SSI1 14 121#define R8A7794_CLK_SSI0 15 122#define R8A7794_CLK_SCU_ALL 17 123#define R8A7794_CLK_SCU_DVC1 18 124#define R8A7794_CLK_SCU_DVC0 19 125#define R8A7794_CLK_SCU_CTU1_MIX1 20 126#define R8A7794_CLK_SCU_CTU0_MIX0 21 127#define R8A7794_CLK_SCU_SRC6 25 128#define R8A7794_CLK_SCU_SRC5 26 129#define R8A7794_CLK_SCU_SRC4 27 130#define R8A7794_CLK_SCU_SRC3 28 131#define R8A7794_CLK_SCU_SRC2 29 132#define R8A7794_CLK_SCU_SRC1 30 133 134/* MSTP11 */ 135#define R8A7794_CLK_SCIFA3 6 136#define R8A7794_CLK_SCIFA4 7 137#define R8A7794_CLK_SCIFA5 8 138 139#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */ 140