1/* $NetBSD: qcom,mmcc-msm8998.h,v 1.1.1.1 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0 */ 4/* 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8998_H 9#define _DT_BINDINGS_CLK_MSM_MMCC_8998_H 10 11#define MMPLL0 0 12#define MMPLL0_OUT_EVEN 1 13#define MMPLL1 2 14#define MMPLL1_OUT_EVEN 3 15#define MMPLL3 4 16#define MMPLL3_OUT_EVEN 5 17#define MMPLL4 6 18#define MMPLL4_OUT_EVEN 7 19#define MMPLL5 8 20#define MMPLL5_OUT_EVEN 9 21#define MMPLL6 10 22#define MMPLL6_OUT_EVEN 11 23#define MMPLL7 12 24#define MMPLL7_OUT_EVEN 13 25#define MMPLL10 14 26#define MMPLL10_OUT_EVEN 15 27#define BYTE0_CLK_SRC 16 28#define BYTE1_CLK_SRC 17 29#define CCI_CLK_SRC 18 30#define CPP_CLK_SRC 19 31#define CSI0_CLK_SRC 20 32#define CSI1_CLK_SRC 21 33#define CSI2_CLK_SRC 22 34#define CSI3_CLK_SRC 23 35#define CSIPHY_CLK_SRC 24 36#define CSI0PHYTIMER_CLK_SRC 25 37#define CSI1PHYTIMER_CLK_SRC 26 38#define CSI2PHYTIMER_CLK_SRC 27 39#define DP_AUX_CLK_SRC 28 40#define DP_CRYPTO_CLK_SRC 29 41#define DP_LINK_CLK_SRC 30 42#define DP_PIXEL_CLK_SRC 31 43#define ESC0_CLK_SRC 32 44#define ESC1_CLK_SRC 33 45#define EXTPCLK_CLK_SRC 34 46#define FD_CORE_CLK_SRC 35 47#define HDMI_CLK_SRC 36 48#define JPEG0_CLK_SRC 37 49#define MAXI_CLK_SRC 38 50#define MCLK0_CLK_SRC 39 51#define MCLK1_CLK_SRC 40 52#define MCLK2_CLK_SRC 41 53#define MCLK3_CLK_SRC 42 54#define MDP_CLK_SRC 43 55#define VSYNC_CLK_SRC 44 56#define AHB_CLK_SRC 45 57#define AXI_CLK_SRC 46 58#define PCLK0_CLK_SRC 47 59#define PCLK1_CLK_SRC 48 60#define ROT_CLK_SRC 49 61#define VIDEO_CORE_CLK_SRC 50 62#define VIDEO_SUBCORE0_CLK_SRC 51 63#define VIDEO_SUBCORE1_CLK_SRC 52 64#define VFE0_CLK_SRC 53 65#define VFE1_CLK_SRC 54 66#define MISC_AHB_CLK 55 67#define VIDEO_CORE_CLK 56 68#define VIDEO_AHB_CLK 57 69#define VIDEO_AXI_CLK 58 70#define VIDEO_MAXI_CLK 59 71#define VIDEO_SUBCORE0_CLK 60 72#define VIDEO_SUBCORE1_CLK 61 73#define MDSS_AHB_CLK 62 74#define MDSS_HDMI_DP_AHB_CLK 63 75#define MDSS_AXI_CLK 64 76#define MDSS_PCLK0_CLK 65 77#define MDSS_PCLK1_CLK 66 78#define MDSS_MDP_CLK 67 79#define MDSS_MDP_LUT_CLK 68 80#define MDSS_EXTPCLK_CLK 69 81#define MDSS_VSYNC_CLK 70 82#define MDSS_HDMI_CLK 71 83#define MDSS_BYTE0_CLK 72 84#define MDSS_BYTE1_CLK 73 85#define MDSS_ESC0_CLK 74 86#define MDSS_ESC1_CLK 75 87#define MDSS_ROT_CLK 76 88#define MDSS_DP_LINK_CLK 77 89#define MDSS_DP_LINK_INTF_CLK 78 90#define MDSS_DP_CRYPTO_CLK 79 91#define MDSS_DP_PIXEL_CLK 80 92#define MDSS_DP_AUX_CLK 81 93#define MDSS_BYTE0_INTF_CLK 82 94#define MDSS_BYTE1_INTF_CLK 83 95#define CAMSS_CSI0PHYTIMER_CLK 84 96#define CAMSS_CSI1PHYTIMER_CLK 85 97#define CAMSS_CSI2PHYTIMER_CLK 86 98#define CAMSS_CSI0_CLK 87 99#define CAMSS_CSI0_AHB_CLK 88 100#define CAMSS_CSI0RDI_CLK 89 101#define CAMSS_CSI0PIX_CLK 90 102#define CAMSS_CSI1_CLK 91 103#define CAMSS_CSI1_AHB_CLK 92 104#define CAMSS_CSI1RDI_CLK 93 105#define CAMSS_CSI1PIX_CLK 94 106#define CAMSS_CSI2_CLK 95 107#define CAMSS_CSI2_AHB_CLK 96 108#define CAMSS_CSI2RDI_CLK 97 109#define CAMSS_CSI2PIX_CLK 98 110#define CAMSS_CSI3_CLK 99 111#define CAMSS_CSI3_AHB_CLK 100 112#define CAMSS_CSI3RDI_CLK 101 113#define CAMSS_CSI3PIX_CLK 102 114#define CAMSS_ISPIF_AHB_CLK 103 115#define CAMSS_CCI_CLK 104 116#define CAMSS_CCI_AHB_CLK 105 117#define CAMSS_MCLK0_CLK 106 118#define CAMSS_MCLK1_CLK 107 119#define CAMSS_MCLK2_CLK 108 120#define CAMSS_MCLK3_CLK 109 121#define CAMSS_TOP_AHB_CLK 110 122#define CAMSS_AHB_CLK 111 123#define CAMSS_MICRO_AHB_CLK 112 124#define CAMSS_JPEG0_CLK 113 125#define CAMSS_JPEG_AHB_CLK 114 126#define CAMSS_JPEG_AXI_CLK 115 127#define CAMSS_VFE0_AHB_CLK 116 128#define CAMSS_VFE1_AHB_CLK 117 129#define CAMSS_VFE0_CLK 118 130#define CAMSS_VFE1_CLK 119 131#define CAMSS_CPP_CLK 120 132#define CAMSS_CPP_AHB_CLK 121 133#define CAMSS_VFE_VBIF_AHB_CLK 122 134#define CAMSS_VFE_VBIF_AXI_CLK 123 135#define CAMSS_CPP_AXI_CLK 124 136#define CAMSS_CPP_VBIF_AHB_CLK 125 137#define CAMSS_CSI_VFE0_CLK 126 138#define CAMSS_CSI_VFE1_CLK 127 139#define CAMSS_VFE0_STREAM_CLK 128 140#define CAMSS_VFE1_STREAM_CLK 129 141#define CAMSS_CPHY_CSID0_CLK 130 142#define CAMSS_CPHY_CSID1_CLK 131 143#define CAMSS_CPHY_CSID2_CLK 132 144#define CAMSS_CPHY_CSID3_CLK 133 145#define CAMSS_CSIPHY0_CLK 134 146#define CAMSS_CSIPHY1_CLK 135 147#define CAMSS_CSIPHY2_CLK 136 148#define FD_CORE_CLK 137 149#define FD_CORE_UAR_CLK 138 150#define FD_AHB_CLK 139 151#define MNOC_AHB_CLK 140 152#define BIMC_SMMU_AHB_CLK 141 153#define BIMC_SMMU_AXI_CLK 142 154#define MNOC_MAXI_CLK 143 155#define VMEM_MAXI_CLK 144 156#define VMEM_AHB_CLK 145 157 158#define SPDM_BCR 0 159#define SPDM_RM_BCR 1 160#define MISC_BCR 2 161#define VIDEO_TOP_BCR 3 162#define THROTTLE_VIDEO_BCR 4 163#define MDSS_BCR 5 164#define THROTTLE_MDSS_BCR 6 165#define CAMSS_PHY0_BCR 7 166#define CAMSS_PHY1_BCR 8 167#define CAMSS_PHY2_BCR 9 168#define CAMSS_CSI0_BCR 10 169#define CAMSS_CSI0RDI_BCR 11 170#define CAMSS_CSI0PIX_BCR 12 171#define CAMSS_CSI1_BCR 13 172#define CAMSS_CSI1RDI_BCR 14 173#define CAMSS_CSI1PIX_BCR 15 174#define CAMSS_CSI2_BCR 16 175#define CAMSS_CSI2RDI_BCR 17 176#define CAMSS_CSI2PIX_BCR 18 177#define CAMSS_CSI3_BCR 19 178#define CAMSS_CSI3RDI_BCR 20 179#define CAMSS_CSI3PIX_BCR 21 180#define CAMSS_ISPIF_BCR 22 181#define CAMSS_CCI_BCR 23 182#define CAMSS_TOP_BCR 24 183#define CAMSS_AHB_BCR 25 184#define CAMSS_MICRO_BCR 26 185#define CAMSS_JPEG_BCR 27 186#define CAMSS_VFE0_BCR 28 187#define CAMSS_VFE1_BCR 29 188#define CAMSS_VFE_VBIF_BCR 30 189#define CAMSS_CPP_TOP_BCR 31 190#define CAMSS_CPP_BCR 32 191#define CAMSS_CSI_VFE0_BCR 33 192#define CAMSS_CSI_VFE1_BCR 34 193#define CAMSS_FD_BCR 35 194#define THROTTLE_CAMSS_BCR 36 195#define MNOCAHB_BCR 37 196#define MNOCAXI_BCR 38 197#define BMIC_SMMU_BCR 39 198#define MNOC_MAXI_BCR 40 199#define VMEM_BCR 41 200#define BTO_BCR 42 201 202#define VIDEO_TOP_GDSC 1 203#define VIDEO_SUBCORE0_GDSC 2 204#define VIDEO_SUBCORE1_GDSC 3 205#define MDSS_GDSC 4 206#define CAMSS_TOP_GDSC 5 207#define CAMSS_VFE0_GDSC 6 208#define CAMSS_VFE1_GDSC 7 209#define CAMSS_CPP_GDSC 8 210#define BIMC_SMMU_GDSC 9 211 212#endif 213