qcom,mmcc-msm8996.h revision 1.1.1.1
1/* $NetBSD: qcom,mmcc-msm8996.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3/* 4 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H 17#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H 18 19#define MMPLL0_EARLY 0 20#define MMPLL0_PLL 1 21#define MMPLL1_EARLY 2 22#define MMPLL1_PLL 3 23#define MMPLL2_EARLY 4 24#define MMPLL2_PLL 5 25#define MMPLL3_EARLY 6 26#define MMPLL3_PLL 7 27#define MMPLL4_EARLY 8 28#define MMPLL4_PLL 9 29#define MMPLL5_EARLY 10 30#define MMPLL5_PLL 11 31#define MMPLL8_EARLY 12 32#define MMPLL8_PLL 13 33#define MMPLL9_EARLY 14 34#define MMPLL9_PLL 15 35#define AHB_CLK_SRC 16 36#define AXI_CLK_SRC 17 37#define MAXI_CLK_SRC 18 38#define DSA_CORE_CLK_SRC 19 39#define GFX3D_CLK_SRC 20 40#define RBBMTIMER_CLK_SRC 21 41#define ISENSE_CLK_SRC 22 42#define RBCPR_CLK_SRC 23 43#define VIDEO_CORE_CLK_SRC 24 44#define VIDEO_SUBCORE0_CLK_SRC 25 45#define VIDEO_SUBCORE1_CLK_SRC 26 46#define PCLK0_CLK_SRC 27 47#define PCLK1_CLK_SRC 28 48#define MDP_CLK_SRC 29 49#define EXTPCLK_CLK_SRC 30 50#define VSYNC_CLK_SRC 31 51#define HDMI_CLK_SRC 32 52#define BYTE0_CLK_SRC 33 53#define BYTE1_CLK_SRC 34 54#define ESC0_CLK_SRC 35 55#define ESC1_CLK_SRC 36 56#define CAMSS_GP0_CLK_SRC 37 57#define CAMSS_GP1_CLK_SRC 38 58#define MCLK0_CLK_SRC 39 59#define MCLK1_CLK_SRC 40 60#define MCLK2_CLK_SRC 41 61#define MCLK3_CLK_SRC 42 62#define CCI_CLK_SRC 43 63#define CSI0PHYTIMER_CLK_SRC 44 64#define CSI1PHYTIMER_CLK_SRC 45 65#define CSI2PHYTIMER_CLK_SRC 46 66#define CSIPHY0_3P_CLK_SRC 47 67#define CSIPHY1_3P_CLK_SRC 48 68#define CSIPHY2_3P_CLK_SRC 49 69#define JPEG0_CLK_SRC 50 70#define JPEG2_CLK_SRC 51 71#define JPEG_DMA_CLK_SRC 52 72#define VFE0_CLK_SRC 53 73#define VFE1_CLK_SRC 54 74#define CPP_CLK_SRC 55 75#define CSI0_CLK_SRC 56 76#define CSI1_CLK_SRC 57 77#define CSI2_CLK_SRC 58 78#define CSI3_CLK_SRC 59 79#define FD_CORE_CLK_SRC 60 80#define MMSS_CXO_CLK 61 81#define MMSS_SLEEPCLK_CLK 62 82#define MMSS_MMAGIC_AHB_CLK 63 83#define MMSS_MMAGIC_CFG_AHB_CLK 64 84#define MMSS_MISC_AHB_CLK 65 85#define MMSS_MISC_CXO_CLK 66 86#define MMSS_BTO_AHB_CLK 67 87#define MMSS_MMAGIC_AXI_CLK 68 88#define MMSS_S0_AXI_CLK 69 89#define MMSS_MMAGIC_MAXI_CLK 70 90#define DSA_CORE_CLK 71 91#define DSA_NOC_CFG_AHB_CLK 72 92#define MMAGIC_CAMSS_AXI_CLK 73 93#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74 94#define THROTTLE_CAMSS_CXO_CLK 75 95#define THROTTLE_CAMSS_AHB_CLK 76 96#define THROTTLE_CAMSS_AXI_CLK 77 97#define SMMU_VFE_AHB_CLK 78 98#define SMMU_VFE_AXI_CLK 79 99#define SMMU_CPP_AHB_CLK 80 100#define SMMU_CPP_AXI_CLK 81 101#define SMMU_JPEG_AHB_CLK 82 102#define SMMU_JPEG_AXI_CLK 83 103#define MMAGIC_MDSS_AXI_CLK 84 104#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85 105#define THROTTLE_MDSS_CXO_CLK 86 106#define THROTTLE_MDSS_AHB_CLK 87 107#define THROTTLE_MDSS_AXI_CLK 88 108#define SMMU_ROT_AHB_CLK 89 109#define SMMU_ROT_AXI_CLK 90 110#define SMMU_MDP_AHB_CLK 91 111#define SMMU_MDP_AXI_CLK 92 112#define MMAGIC_VIDEO_AXI_CLK 93 113#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94 114#define THROTTLE_VIDEO_CXO_CLK 95 115#define THROTTLE_VIDEO_AHB_CLK 96 116#define THROTTLE_VIDEO_AXI_CLK 97 117#define SMMU_VIDEO_AHB_CLK 98 118#define SMMU_VIDEO_AXI_CLK 99 119#define MMAGIC_BIMC_AXI_CLK 100 120#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101 121#define GPU_GX_GFX3D_CLK 102 122#define GPU_GX_RBBMTIMER_CLK 103 123#define GPU_AHB_CLK 104 124#define GPU_AON_ISENSE_CLK 105 125#define VMEM_MAXI_CLK 106 126#define VMEM_AHB_CLK 107 127#define MMSS_RBCPR_CLK 108 128#define MMSS_RBCPR_AHB_CLK 109 129#define VIDEO_CORE_CLK 110 130#define VIDEO_AXI_CLK 111 131#define VIDEO_MAXI_CLK 112 132#define VIDEO_AHB_CLK 113 133#define VIDEO_SUBCORE0_CLK 114 134#define VIDEO_SUBCORE1_CLK 115 135#define MDSS_AHB_CLK 116 136#define MDSS_HDMI_AHB_CLK 117 137#define MDSS_AXI_CLK 118 138#define MDSS_PCLK0_CLK 119 139#define MDSS_PCLK1_CLK 120 140#define MDSS_MDP_CLK 121 141#define MDSS_EXTPCLK_CLK 122 142#define MDSS_VSYNC_CLK 123 143#define MDSS_HDMI_CLK 124 144#define MDSS_BYTE0_CLK 125 145#define MDSS_BYTE1_CLK 126 146#define MDSS_ESC0_CLK 127 147#define MDSS_ESC1_CLK 128 148#define CAMSS_TOP_AHB_CLK 129 149#define CAMSS_AHB_CLK 130 150#define CAMSS_MICRO_AHB_CLK 131 151#define CAMSS_GP0_CLK 132 152#define CAMSS_GP1_CLK 133 153#define CAMSS_MCLK0_CLK 134 154#define CAMSS_MCLK1_CLK 135 155#define CAMSS_MCLK2_CLK 136 156#define CAMSS_MCLK3_CLK 137 157#define CAMSS_CCI_CLK 138 158#define CAMSS_CCI_AHB_CLK 139 159#define CAMSS_CSI0PHYTIMER_CLK 140 160#define CAMSS_CSI1PHYTIMER_CLK 141 161#define CAMSS_CSI2PHYTIMER_CLK 142 162#define CAMSS_CSIPHY0_3P_CLK 143 163#define CAMSS_CSIPHY1_3P_CLK 144 164#define CAMSS_CSIPHY2_3P_CLK 145 165#define CAMSS_JPEG0_CLK 146 166#define CAMSS_JPEG2_CLK 147 167#define CAMSS_JPEG_DMA_CLK 148 168#define CAMSS_JPEG_AHB_CLK 149 169#define CAMSS_JPEG_AXI_CLK 150 170#define CAMSS_VFE_AHB_CLK 151 171#define CAMSS_VFE_AXI_CLK 152 172#define CAMSS_VFE0_CLK 153 173#define CAMSS_VFE0_STREAM_CLK 154 174#define CAMSS_VFE0_AHB_CLK 155 175#define CAMSS_VFE1_CLK 156 176#define CAMSS_VFE1_STREAM_CLK 157 177#define CAMSS_VFE1_AHB_CLK 158 178#define CAMSS_CSI_VFE0_CLK 159 179#define CAMSS_CSI_VFE1_CLK 160 180#define CAMSS_CPP_VBIF_AHB_CLK 161 181#define CAMSS_CPP_AXI_CLK 162 182#define CAMSS_CPP_CLK 163 183#define CAMSS_CPP_AHB_CLK 164 184#define CAMSS_CSI0_CLK 165 185#define CAMSS_CSI0_AHB_CLK 166 186#define CAMSS_CSI0PHY_CLK 167 187#define CAMSS_CSI0RDI_CLK 168 188#define CAMSS_CSI0PIX_CLK 169 189#define CAMSS_CSI1_CLK 170 190#define CAMSS_CSI1_AHB_CLK 171 191#define CAMSS_CSI1PHY_CLK 172 192#define CAMSS_CSI1RDI_CLK 173 193#define CAMSS_CSI1PIX_CLK 174 194#define CAMSS_CSI2_CLK 175 195#define CAMSS_CSI2_AHB_CLK 176 196#define CAMSS_CSI2PHY_CLK 177 197#define CAMSS_CSI2RDI_CLK 178 198#define CAMSS_CSI2PIX_CLK 179 199#define CAMSS_CSI3_CLK 180 200#define CAMSS_CSI3_AHB_CLK 181 201#define CAMSS_CSI3PHY_CLK 182 202#define CAMSS_CSI3RDI_CLK 183 203#define CAMSS_CSI3PIX_CLK 184 204#define CAMSS_ISPIF_AHB_CLK 185 205#define FD_CORE_CLK 186 206#define FD_CORE_UAR_CLK 187 207#define FD_AHB_CLK 188 208#define MMSS_SPDM_CSI0_CLK 189 209#define MMSS_SPDM_JPEG_DMA_CLK 190 210#define MMSS_SPDM_CPP_CLK 191 211#define MMSS_SPDM_PCLK0_CLK 192 212#define MMSS_SPDM_AHB_CLK 193 213#define MMSS_SPDM_GFX3D_CLK 194 214#define MMSS_SPDM_PCLK1_CLK 195 215#define MMSS_SPDM_JPEG2_CLK 196 216#define MMSS_SPDM_DEBUG_CLK 197 217#define MMSS_SPDM_VFE1_CLK 198 218#define MMSS_SPDM_VFE0_CLK 199 219#define MMSS_SPDM_VIDEO_CORE_CLK 200 220#define MMSS_SPDM_AXI_CLK 201 221#define MMSS_SPDM_MDP_CLK 202 222#define MMSS_SPDM_JPEG0_CLK 203 223#define MMSS_SPDM_RM_AXI_CLK 204 224#define MMSS_SPDM_RM_MAXI_CLK 205 225 226#define MMAGICAHB_BCR 0 227#define MMAGIC_CFG_BCR 1 228#define MISC_BCR 2 229#define BTO_BCR 3 230#define MMAGICAXI_BCR 4 231#define MMAGICMAXI_BCR 5 232#define DSA_BCR 6 233#define MMAGIC_CAMSS_BCR 7 234#define THROTTLE_CAMSS_BCR 8 235#define SMMU_VFE_BCR 9 236#define SMMU_CPP_BCR 10 237#define SMMU_JPEG_BCR 11 238#define MMAGIC_MDSS_BCR 12 239#define THROTTLE_MDSS_BCR 13 240#define SMMU_ROT_BCR 14 241#define SMMU_MDP_BCR 15 242#define MMAGIC_VIDEO_BCR 16 243#define THROTTLE_VIDEO_BCR 17 244#define SMMU_VIDEO_BCR 18 245#define MMAGIC_BIMC_BCR 19 246#define GPU_GX_BCR 20 247#define GPU_BCR 21 248#define GPU_AON_BCR 22 249#define VMEM_BCR 23 250#define MMSS_RBCPR_BCR 24 251#define VIDEO_BCR 25 252#define MDSS_BCR 26 253#define CAMSS_TOP_BCR 27 254#define CAMSS_AHB_BCR 28 255#define CAMSS_MICRO_BCR 29 256#define CAMSS_CCI_BCR 30 257#define CAMSS_PHY0_BCR 31 258#define CAMSS_PHY1_BCR 32 259#define CAMSS_PHY2_BCR 33 260#define CAMSS_CSIPHY0_3P_BCR 34 261#define CAMSS_CSIPHY1_3P_BCR 35 262#define CAMSS_CSIPHY2_3P_BCR 36 263#define CAMSS_JPEG_BCR 37 264#define CAMSS_VFE_BCR 38 265#define CAMSS_VFE0_BCR 39 266#define CAMSS_VFE1_BCR 40 267#define CAMSS_CSI_VFE0_BCR 41 268#define CAMSS_CSI_VFE1_BCR 42 269#define CAMSS_CPP_TOP_BCR 43 270#define CAMSS_CPP_BCR 44 271#define CAMSS_CSI0_BCR 45 272#define CAMSS_CSI0RDI_BCR 46 273#define CAMSS_CSI0PIX_BCR 47 274#define CAMSS_CSI1_BCR 48 275#define CAMSS_CSI1RDI_BCR 49 276#define CAMSS_CSI1PIX_BCR 50 277#define CAMSS_CSI2_BCR 51 278#define CAMSS_CSI2RDI_BCR 52 279#define CAMSS_CSI2PIX_BCR 53 280#define CAMSS_CSI3_BCR 54 281#define CAMSS_CSI3RDI_BCR 55 282#define CAMSS_CSI3PIX_BCR 56 283#define CAMSS_ISPIF_BCR 57 284#define FD_BCR 58 285#define MMSS_SPDM_RM_BCR 59 286 287/* Indexes for GDSCs */ 288#define MMAGIC_VIDEO_GDSC 0 289#define MMAGIC_MDSS_GDSC 1 290#define MMAGIC_CAMSS_GDSC 2 291#define GPU_GDSC 3 292#define VENUS_GDSC 4 293#define VENUS_CORE0_GDSC 5 294#define VENUS_CORE1_GDSC 6 295#define CAMSS_GDSC 7 296#define VFE0_GDSC 8 297#define VFE1_GDSC 9 298#define JPEG_GDSC 10 299#define CPP_GDSC 11 300#define FD_GDSC 12 301#define MDSS_GDSC 13 302#define GPU_GX_GDSC 14 303#define MMAGIC_BIMC_GDSC 15 304 305#endif 306