1/* $NetBSD: qcom,mmcc-msm8996.h,v 1.1.1.2 2020/01/03 14:33:04 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-only */ 4/* 5 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 6 */ 7 8#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H 9#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H 10 11#define MMPLL0_EARLY 0 12#define MMPLL0_PLL 1 13#define MMPLL1_EARLY 2 14#define MMPLL1_PLL 3 15#define MMPLL2_EARLY 4 16#define MMPLL2_PLL 5 17#define MMPLL3_EARLY 6 18#define MMPLL3_PLL 7 19#define MMPLL4_EARLY 8 20#define MMPLL4_PLL 9 21#define MMPLL5_EARLY 10 22#define MMPLL5_PLL 11 23#define MMPLL8_EARLY 12 24#define MMPLL8_PLL 13 25#define MMPLL9_EARLY 14 26#define MMPLL9_PLL 15 27#define AHB_CLK_SRC 16 28#define AXI_CLK_SRC 17 29#define MAXI_CLK_SRC 18 30#define DSA_CORE_CLK_SRC 19 31#define GFX3D_CLK_SRC 20 32#define RBBMTIMER_CLK_SRC 21 33#define ISENSE_CLK_SRC 22 34#define RBCPR_CLK_SRC 23 35#define VIDEO_CORE_CLK_SRC 24 36#define VIDEO_SUBCORE0_CLK_SRC 25 37#define VIDEO_SUBCORE1_CLK_SRC 26 38#define PCLK0_CLK_SRC 27 39#define PCLK1_CLK_SRC 28 40#define MDP_CLK_SRC 29 41#define EXTPCLK_CLK_SRC 30 42#define VSYNC_CLK_SRC 31 43#define HDMI_CLK_SRC 32 44#define BYTE0_CLK_SRC 33 45#define BYTE1_CLK_SRC 34 46#define ESC0_CLK_SRC 35 47#define ESC1_CLK_SRC 36 48#define CAMSS_GP0_CLK_SRC 37 49#define CAMSS_GP1_CLK_SRC 38 50#define MCLK0_CLK_SRC 39 51#define MCLK1_CLK_SRC 40 52#define MCLK2_CLK_SRC 41 53#define MCLK3_CLK_SRC 42 54#define CCI_CLK_SRC 43 55#define CSI0PHYTIMER_CLK_SRC 44 56#define CSI1PHYTIMER_CLK_SRC 45 57#define CSI2PHYTIMER_CLK_SRC 46 58#define CSIPHY0_3P_CLK_SRC 47 59#define CSIPHY1_3P_CLK_SRC 48 60#define CSIPHY2_3P_CLK_SRC 49 61#define JPEG0_CLK_SRC 50 62#define JPEG2_CLK_SRC 51 63#define JPEG_DMA_CLK_SRC 52 64#define VFE0_CLK_SRC 53 65#define VFE1_CLK_SRC 54 66#define CPP_CLK_SRC 55 67#define CSI0_CLK_SRC 56 68#define CSI1_CLK_SRC 57 69#define CSI2_CLK_SRC 58 70#define CSI3_CLK_SRC 59 71#define FD_CORE_CLK_SRC 60 72#define MMSS_CXO_CLK 61 73#define MMSS_SLEEPCLK_CLK 62 74#define MMSS_MMAGIC_AHB_CLK 63 75#define MMSS_MMAGIC_CFG_AHB_CLK 64 76#define MMSS_MISC_AHB_CLK 65 77#define MMSS_MISC_CXO_CLK 66 78#define MMSS_BTO_AHB_CLK 67 79#define MMSS_MMAGIC_AXI_CLK 68 80#define MMSS_S0_AXI_CLK 69 81#define MMSS_MMAGIC_MAXI_CLK 70 82#define DSA_CORE_CLK 71 83#define DSA_NOC_CFG_AHB_CLK 72 84#define MMAGIC_CAMSS_AXI_CLK 73 85#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74 86#define THROTTLE_CAMSS_CXO_CLK 75 87#define THROTTLE_CAMSS_AHB_CLK 76 88#define THROTTLE_CAMSS_AXI_CLK 77 89#define SMMU_VFE_AHB_CLK 78 90#define SMMU_VFE_AXI_CLK 79 91#define SMMU_CPP_AHB_CLK 80 92#define SMMU_CPP_AXI_CLK 81 93#define SMMU_JPEG_AHB_CLK 82 94#define SMMU_JPEG_AXI_CLK 83 95#define MMAGIC_MDSS_AXI_CLK 84 96#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85 97#define THROTTLE_MDSS_CXO_CLK 86 98#define THROTTLE_MDSS_AHB_CLK 87 99#define THROTTLE_MDSS_AXI_CLK 88 100#define SMMU_ROT_AHB_CLK 89 101#define SMMU_ROT_AXI_CLK 90 102#define SMMU_MDP_AHB_CLK 91 103#define SMMU_MDP_AXI_CLK 92 104#define MMAGIC_VIDEO_AXI_CLK 93 105#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94 106#define THROTTLE_VIDEO_CXO_CLK 95 107#define THROTTLE_VIDEO_AHB_CLK 96 108#define THROTTLE_VIDEO_AXI_CLK 97 109#define SMMU_VIDEO_AHB_CLK 98 110#define SMMU_VIDEO_AXI_CLK 99 111#define MMAGIC_BIMC_AXI_CLK 100 112#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101 113#define GPU_GX_GFX3D_CLK 102 114#define GPU_GX_RBBMTIMER_CLK 103 115#define GPU_AHB_CLK 104 116#define GPU_AON_ISENSE_CLK 105 117#define VMEM_MAXI_CLK 106 118#define VMEM_AHB_CLK 107 119#define MMSS_RBCPR_CLK 108 120#define MMSS_RBCPR_AHB_CLK 109 121#define VIDEO_CORE_CLK 110 122#define VIDEO_AXI_CLK 111 123#define VIDEO_MAXI_CLK 112 124#define VIDEO_AHB_CLK 113 125#define VIDEO_SUBCORE0_CLK 114 126#define VIDEO_SUBCORE1_CLK 115 127#define MDSS_AHB_CLK 116 128#define MDSS_HDMI_AHB_CLK 117 129#define MDSS_AXI_CLK 118 130#define MDSS_PCLK0_CLK 119 131#define MDSS_PCLK1_CLK 120 132#define MDSS_MDP_CLK 121 133#define MDSS_EXTPCLK_CLK 122 134#define MDSS_VSYNC_CLK 123 135#define MDSS_HDMI_CLK 124 136#define MDSS_BYTE0_CLK 125 137#define MDSS_BYTE1_CLK 126 138#define MDSS_ESC0_CLK 127 139#define MDSS_ESC1_CLK 128 140#define CAMSS_TOP_AHB_CLK 129 141#define CAMSS_AHB_CLK 130 142#define CAMSS_MICRO_AHB_CLK 131 143#define CAMSS_GP0_CLK 132 144#define CAMSS_GP1_CLK 133 145#define CAMSS_MCLK0_CLK 134 146#define CAMSS_MCLK1_CLK 135 147#define CAMSS_MCLK2_CLK 136 148#define CAMSS_MCLK3_CLK 137 149#define CAMSS_CCI_CLK 138 150#define CAMSS_CCI_AHB_CLK 139 151#define CAMSS_CSI0PHYTIMER_CLK 140 152#define CAMSS_CSI1PHYTIMER_CLK 141 153#define CAMSS_CSI2PHYTIMER_CLK 142 154#define CAMSS_CSIPHY0_3P_CLK 143 155#define CAMSS_CSIPHY1_3P_CLK 144 156#define CAMSS_CSIPHY2_3P_CLK 145 157#define CAMSS_JPEG0_CLK 146 158#define CAMSS_JPEG2_CLK 147 159#define CAMSS_JPEG_DMA_CLK 148 160#define CAMSS_JPEG_AHB_CLK 149 161#define CAMSS_JPEG_AXI_CLK 150 162#define CAMSS_VFE_AHB_CLK 151 163#define CAMSS_VFE_AXI_CLK 152 164#define CAMSS_VFE0_CLK 153 165#define CAMSS_VFE0_STREAM_CLK 154 166#define CAMSS_VFE0_AHB_CLK 155 167#define CAMSS_VFE1_CLK 156 168#define CAMSS_VFE1_STREAM_CLK 157 169#define CAMSS_VFE1_AHB_CLK 158 170#define CAMSS_CSI_VFE0_CLK 159 171#define CAMSS_CSI_VFE1_CLK 160 172#define CAMSS_CPP_VBIF_AHB_CLK 161 173#define CAMSS_CPP_AXI_CLK 162 174#define CAMSS_CPP_CLK 163 175#define CAMSS_CPP_AHB_CLK 164 176#define CAMSS_CSI0_CLK 165 177#define CAMSS_CSI0_AHB_CLK 166 178#define CAMSS_CSI0PHY_CLK 167 179#define CAMSS_CSI0RDI_CLK 168 180#define CAMSS_CSI0PIX_CLK 169 181#define CAMSS_CSI1_CLK 170 182#define CAMSS_CSI1_AHB_CLK 171 183#define CAMSS_CSI1PHY_CLK 172 184#define CAMSS_CSI1RDI_CLK 173 185#define CAMSS_CSI1PIX_CLK 174 186#define CAMSS_CSI2_CLK 175 187#define CAMSS_CSI2_AHB_CLK 176 188#define CAMSS_CSI2PHY_CLK 177 189#define CAMSS_CSI2RDI_CLK 178 190#define CAMSS_CSI2PIX_CLK 179 191#define CAMSS_CSI3_CLK 180 192#define CAMSS_CSI3_AHB_CLK 181 193#define CAMSS_CSI3PHY_CLK 182 194#define CAMSS_CSI3RDI_CLK 183 195#define CAMSS_CSI3PIX_CLK 184 196#define CAMSS_ISPIF_AHB_CLK 185 197#define FD_CORE_CLK 186 198#define FD_CORE_UAR_CLK 187 199#define FD_AHB_CLK 188 200#define MMSS_SPDM_CSI0_CLK 189 201#define MMSS_SPDM_JPEG_DMA_CLK 190 202#define MMSS_SPDM_CPP_CLK 191 203#define MMSS_SPDM_PCLK0_CLK 192 204#define MMSS_SPDM_AHB_CLK 193 205#define MMSS_SPDM_GFX3D_CLK 194 206#define MMSS_SPDM_PCLK1_CLK 195 207#define MMSS_SPDM_JPEG2_CLK 196 208#define MMSS_SPDM_DEBUG_CLK 197 209#define MMSS_SPDM_VFE1_CLK 198 210#define MMSS_SPDM_VFE0_CLK 199 211#define MMSS_SPDM_VIDEO_CORE_CLK 200 212#define MMSS_SPDM_AXI_CLK 201 213#define MMSS_SPDM_MDP_CLK 202 214#define MMSS_SPDM_JPEG0_CLK 203 215#define MMSS_SPDM_RM_AXI_CLK 204 216#define MMSS_SPDM_RM_MAXI_CLK 205 217 218#define MMAGICAHB_BCR 0 219#define MMAGIC_CFG_BCR 1 220#define MISC_BCR 2 221#define BTO_BCR 3 222#define MMAGICAXI_BCR 4 223#define MMAGICMAXI_BCR 5 224#define DSA_BCR 6 225#define MMAGIC_CAMSS_BCR 7 226#define THROTTLE_CAMSS_BCR 8 227#define SMMU_VFE_BCR 9 228#define SMMU_CPP_BCR 10 229#define SMMU_JPEG_BCR 11 230#define MMAGIC_MDSS_BCR 12 231#define THROTTLE_MDSS_BCR 13 232#define SMMU_ROT_BCR 14 233#define SMMU_MDP_BCR 15 234#define MMAGIC_VIDEO_BCR 16 235#define THROTTLE_VIDEO_BCR 17 236#define SMMU_VIDEO_BCR 18 237#define MMAGIC_BIMC_BCR 19 238#define GPU_GX_BCR 20 239#define GPU_BCR 21 240#define GPU_AON_BCR 22 241#define VMEM_BCR 23 242#define MMSS_RBCPR_BCR 24 243#define VIDEO_BCR 25 244#define MDSS_BCR 26 245#define CAMSS_TOP_BCR 27 246#define CAMSS_AHB_BCR 28 247#define CAMSS_MICRO_BCR 29 248#define CAMSS_CCI_BCR 30 249#define CAMSS_PHY0_BCR 31 250#define CAMSS_PHY1_BCR 32 251#define CAMSS_PHY2_BCR 33 252#define CAMSS_CSIPHY0_3P_BCR 34 253#define CAMSS_CSIPHY1_3P_BCR 35 254#define CAMSS_CSIPHY2_3P_BCR 36 255#define CAMSS_JPEG_BCR 37 256#define CAMSS_VFE_BCR 38 257#define CAMSS_VFE0_BCR 39 258#define CAMSS_VFE1_BCR 40 259#define CAMSS_CSI_VFE0_BCR 41 260#define CAMSS_CSI_VFE1_BCR 42 261#define CAMSS_CPP_TOP_BCR 43 262#define CAMSS_CPP_BCR 44 263#define CAMSS_CSI0_BCR 45 264#define CAMSS_CSI0RDI_BCR 46 265#define CAMSS_CSI0PIX_BCR 47 266#define CAMSS_CSI1_BCR 48 267#define CAMSS_CSI1RDI_BCR 49 268#define CAMSS_CSI1PIX_BCR 50 269#define CAMSS_CSI2_BCR 51 270#define CAMSS_CSI2RDI_BCR 52 271#define CAMSS_CSI2PIX_BCR 53 272#define CAMSS_CSI3_BCR 54 273#define CAMSS_CSI3RDI_BCR 55 274#define CAMSS_CSI3PIX_BCR 56 275#define CAMSS_ISPIF_BCR 57 276#define FD_BCR 58 277#define MMSS_SPDM_RM_BCR 59 278 279/* Indexes for GDSCs */ 280#define MMAGIC_VIDEO_GDSC 0 281#define MMAGIC_MDSS_GDSC 1 282#define MMAGIC_CAMSS_GDSC 2 283#define GPU_GDSC 3 284#define VENUS_GDSC 4 285#define VENUS_CORE0_GDSC 5 286#define VENUS_CORE1_GDSC 6 287#define CAMSS_GDSC 7 288#define VFE0_GDSC 8 289#define VFE1_GDSC 9 290#define JPEG_GDSC 10 291#define CPP_GDSC 11 292#define FD_GDSC 12 293#define MDSS_GDSC 13 294#define GPU_GX_GDSC 14 295#define MMAGIC_BIMC_GDSC 15 296 297#endif 298