1/* $NetBSD: qcom,gcc-mdm9607.h,v 1.1.1.1 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ 4/* 5 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 6 */ 7 8#ifndef _DT_BINDINGS_CLK_MSM_GCC_9607_H 9#define _DT_BINDINGS_CLK_MSM_GCC_9607_H 10 11#define GPLL0 0 12#define GPLL0_EARLY 1 13#define GPLL1 2 14#define GPLL1_VOTE 3 15#define GPLL2 4 16#define GPLL2_EARLY 5 17#define PCNOC_BFDCD_CLK_SRC 6 18#define SYSTEM_NOC_BFDCD_CLK_SRC 7 19#define GCC_SMMU_CFG_CLK 8 20#define APSS_AHB_CLK_SRC 9 21#define GCC_QDSS_DAP_CLK 10 22#define BLSP1_QUP1_I2C_APPS_CLK_SRC 11 23#define BLSP1_QUP1_SPI_APPS_CLK_SRC 12 24#define BLSP1_QUP2_I2C_APPS_CLK_SRC 13 25#define BLSP1_QUP2_SPI_APPS_CLK_SRC 14 26#define BLSP1_QUP3_I2C_APPS_CLK_SRC 15 27#define BLSP1_QUP3_SPI_APPS_CLK_SRC 16 28#define BLSP1_QUP4_I2C_APPS_CLK_SRC 17 29#define BLSP1_QUP4_SPI_APPS_CLK_SRC 18 30#define BLSP1_QUP5_I2C_APPS_CLK_SRC 19 31#define BLSP1_QUP5_SPI_APPS_CLK_SRC 20 32#define BLSP1_QUP6_I2C_APPS_CLK_SRC 21 33#define BLSP1_QUP6_SPI_APPS_CLK_SRC 22 34#define BLSP1_UART1_APPS_CLK_SRC 23 35#define BLSP1_UART2_APPS_CLK_SRC 24 36#define CRYPTO_CLK_SRC 25 37#define GP1_CLK_SRC 26 38#define GP2_CLK_SRC 27 39#define GP3_CLK_SRC 28 40#define PDM2_CLK_SRC 29 41#define SDCC1_APPS_CLK_SRC 30 42#define SDCC2_APPS_CLK_SRC 31 43#define APSS_TCU_CLK_SRC 32 44#define USB_HS_SYSTEM_CLK_SRC 33 45#define GCC_BLSP1_AHB_CLK 34 46#define GCC_BLSP1_SLEEP_CLK 35 47#define GCC_BLSP1_QUP1_I2C_APPS_CLK 36 48#define GCC_BLSP1_QUP1_SPI_APPS_CLK 37 49#define GCC_BLSP1_QUP2_I2C_APPS_CLK 38 50#define GCC_BLSP1_QUP2_SPI_APPS_CLK 39 51#define GCC_BLSP1_QUP3_I2C_APPS_CLK 40 52#define GCC_BLSP1_QUP3_SPI_APPS_CLK 41 53#define GCC_BLSP1_QUP4_I2C_APPS_CLK 42 54#define GCC_BLSP1_QUP4_SPI_APPS_CLK 43 55#define GCC_BLSP1_QUP5_I2C_APPS_CLK 44 56#define GCC_BLSP1_QUP5_SPI_APPS_CLK 45 57#define GCC_BLSP1_QUP6_I2C_APPS_CLK 46 58#define GCC_BLSP1_QUP6_SPI_APPS_CLK 47 59#define GCC_BLSP1_UART1_APPS_CLK 48 60#define GCC_BLSP1_UART2_APPS_CLK 49 61#define GCC_BOOT_ROM_AHB_CLK 50 62#define GCC_CRYPTO_AHB_CLK 51 63#define GCC_CRYPTO_AXI_CLK 52 64#define GCC_CRYPTO_CLK 53 65#define GCC_GP1_CLK 54 66#define GCC_GP2_CLK 55 67#define GCC_GP3_CLK 56 68#define GCC_MSS_CFG_AHB_CLK 57 69#define GCC_PDM2_CLK 58 70#define GCC_PDM_AHB_CLK 59 71#define GCC_PRNG_AHB_CLK 60 72#define GCC_SDCC1_AHB_CLK 61 73#define GCC_SDCC1_APPS_CLK 62 74#define GCC_SDCC2_AHB_CLK 63 75#define GCC_SDCC2_APPS_CLK 64 76#define GCC_USB2A_PHY_SLEEP_CLK 65 77#define GCC_USB_HS_AHB_CLK 66 78#define GCC_USB_HS_SYSTEM_CLK 67 79#define GCC_APSS_TCU_CLK 68 80#define GCC_MSS_Q6_BIMC_AXI_CLK 69 81#define BIMC_PLL 70 82#define BIMC_PLL_VOTE 71 83#define BIMC_DDR_CLK_SRC 72 84#define BLSP1_UART3_APPS_CLK_SRC 73 85#define BLSP1_UART4_APPS_CLK_SRC 74 86#define BLSP1_UART5_APPS_CLK_SRC 75 87#define BLSP1_UART6_APPS_CLK_SRC 76 88#define GCC_BLSP1_UART3_APPS_CLK 77 89#define GCC_BLSP1_UART4_APPS_CLK 78 90#define GCC_BLSP1_UART5_APPS_CLK 79 91#define GCC_BLSP1_UART6_APPS_CLK 80 92#define GCC_APSS_AHB_CLK 81 93#define GCC_APSS_AXI_CLK 82 94#define GCC_USB_HS_PHY_CFG_AHB_CLK 83 95#define GCC_USB_HSIC_CLK_SRC 84 96#define GCC_USB_HSIC_IO_CAL_CLK_SRC 85 97#define GCC_USB_HSIC_SYSTEM_CLK_SRC 86 98 99/* Resets */ 100#define USB2_HS_PHY_ONLY_BCR 0 101#define QUSB2_PHY_BCR 1 102#define GCC_MSS_RESTART 2 103#define USB_HS_HSIC_BCR 3 104#define USB_HS_BCR 4 105 106#endif 107