1/* $NetBSD: mt6765-clk.h,v 1.1.1.1 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0 */ 4 5#ifndef _DT_BINDINGS_CLK_MT6765_H 6#define _DT_BINDINGS_CLK_MT6765_H 7 8/* FIX Clks */ 9#define CLK_TOP_CLK26M 0 10 11/* APMIXEDSYS */ 12#define CLK_APMIXED_ARMPLL_L 0 13#define CLK_APMIXED_ARMPLL 1 14#define CLK_APMIXED_CCIPLL 2 15#define CLK_APMIXED_MAINPLL 3 16#define CLK_APMIXED_MFGPLL 4 17#define CLK_APMIXED_MMPLL 5 18#define CLK_APMIXED_UNIV2PLL 6 19#define CLK_APMIXED_MSDCPLL 7 20#define CLK_APMIXED_APLL1 8 21#define CLK_APMIXED_MPLL 9 22#define CLK_APMIXED_ULPOSC1 10 23#define CLK_APMIXED_ULPOSC2 11 24#define CLK_APMIXED_SSUSB26M 12 25#define CLK_APMIXED_APPLL26M 13 26#define CLK_APMIXED_MIPIC0_26M 14 27#define CLK_APMIXED_MDPLLGP26M 15 28#define CLK_APMIXED_MMSYS_F26M 16 29#define CLK_APMIXED_UFS26M 17 30#define CLK_APMIXED_MIPIC1_26M 18 31#define CLK_APMIXED_MEMPLL26M 19 32#define CLK_APMIXED_CLKSQ_LVPLL_26M 20 33#define CLK_APMIXED_MIPID0_26M 21 34#define CLK_APMIXED_NR_CLK 22 35 36/* TOPCKGEN */ 37#define CLK_TOP_SYSPLL 0 38#define CLK_TOP_SYSPLL_D2 1 39#define CLK_TOP_SYSPLL1_D2 2 40#define CLK_TOP_SYSPLL1_D4 3 41#define CLK_TOP_SYSPLL1_D8 4 42#define CLK_TOP_SYSPLL1_D16 5 43#define CLK_TOP_SYSPLL_D3 6 44#define CLK_TOP_SYSPLL2_D2 7 45#define CLK_TOP_SYSPLL2_D4 8 46#define CLK_TOP_SYSPLL2_D8 9 47#define CLK_TOP_SYSPLL_D5 10 48#define CLK_TOP_SYSPLL3_D2 11 49#define CLK_TOP_SYSPLL3_D4 12 50#define CLK_TOP_SYSPLL_D7 13 51#define CLK_TOP_SYSPLL4_D2 14 52#define CLK_TOP_SYSPLL4_D4 15 53#define CLK_TOP_USB20_192M 16 54#define CLK_TOP_USB20_192M_D4 17 55#define CLK_TOP_USB20_192M_D8 18 56#define CLK_TOP_USB20_192M_D16 19 57#define CLK_TOP_USB20_192M_D32 20 58#define CLK_TOP_UNIVPLL 21 59#define CLK_TOP_UNIVPLL_D2 22 60#define CLK_TOP_UNIVPLL1_D2 23 61#define CLK_TOP_UNIVPLL1_D4 24 62#define CLK_TOP_UNIVPLL_D3 25 63#define CLK_TOP_UNIVPLL2_D2 26 64#define CLK_TOP_UNIVPLL2_D4 27 65#define CLK_TOP_UNIVPLL2_D8 28 66#define CLK_TOP_UNIVPLL2_D32 29 67#define CLK_TOP_UNIVPLL_D5 30 68#define CLK_TOP_UNIVPLL3_D2 31 69#define CLK_TOP_UNIVPLL3_D4 32 70#define CLK_TOP_MMPLL 33 71#define CLK_TOP_MMPLL_D2 34 72#define CLK_TOP_MPLL 35 73#define CLK_TOP_DA_MPLL_104M_DIV 36 74#define CLK_TOP_DA_MPLL_52M_DIV 37 75#define CLK_TOP_MFGPLL 38 76#define CLK_TOP_MSDCPLL 39 77#define CLK_TOP_MSDCPLL_D2 40 78#define CLK_TOP_APLL1 41 79#define CLK_TOP_APLL1_D2 42 80#define CLK_TOP_APLL1_D4 43 81#define CLK_TOP_APLL1_D8 44 82#define CLK_TOP_ULPOSC1 45 83#define CLK_TOP_ULPOSC1_D2 46 84#define CLK_TOP_ULPOSC1_D4 47 85#define CLK_TOP_ULPOSC1_D8 48 86#define CLK_TOP_ULPOSC1_D16 49 87#define CLK_TOP_ULPOSC1_D32 50 88#define CLK_TOP_DMPLL 51 89#define CLK_TOP_F_FRTC 52 90#define CLK_TOP_F_F26M 53 91#define CLK_TOP_AXI 54 92#define CLK_TOP_MM 55 93#define CLK_TOP_SCP 56 94#define CLK_TOP_MFG 57 95#define CLK_TOP_F_FUART 58 96#define CLK_TOP_SPI 59 97#define CLK_TOP_MSDC50_0 60 98#define CLK_TOP_MSDC30_1 61 99#define CLK_TOP_AUDIO 62 100#define CLK_TOP_AUD_1 63 101#define CLK_TOP_AUD_ENGEN1 64 102#define CLK_TOP_F_FDISP_PWM 65 103#define CLK_TOP_SSPM 66 104#define CLK_TOP_DXCC 67 105#define CLK_TOP_I2C 68 106#define CLK_TOP_F_FPWM 69 107#define CLK_TOP_F_FSENINF 70 108#define CLK_TOP_AES_FDE 71 109#define CLK_TOP_F_BIST2FPC 72 110#define CLK_TOP_ARMPLL_DIVIDER_PLL0 73 111#define CLK_TOP_ARMPLL_DIVIDER_PLL1 74 112#define CLK_TOP_ARMPLL_DIVIDER_PLL2 75 113#define CLK_TOP_DA_USB20_48M_DIV 76 114#define CLK_TOP_DA_UNIV_48M_DIV 77 115#define CLK_TOP_APLL12_DIV0 78 116#define CLK_TOP_APLL12_DIV1 79 117#define CLK_TOP_APLL12_DIV2 80 118#define CLK_TOP_APLL12_DIV3 81 119#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82 120#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83 121#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84 122#define CLK_TOP_FMEM_OCC_DRC_EN 85 123#define CLK_TOP_USB20_48M_EN 86 124#define CLK_TOP_UNIVPLL_48M_EN 87 125#define CLK_TOP_MPLL_104M_EN 88 126#define CLK_TOP_MPLL_52M_EN 89 127#define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90 128#define CLK_TOP_F_BIST2FPC_EN 91 129#define CLK_TOP_MD_32K 92 130#define CLK_TOP_MD_26M 93 131#define CLK_TOP_MD2_32K 94 132#define CLK_TOP_MD2_26M 95 133#define CLK_TOP_AXI_SEL 96 134#define CLK_TOP_MEM_SEL 97 135#define CLK_TOP_MM_SEL 98 136#define CLK_TOP_SCP_SEL 99 137#define CLK_TOP_MFG_SEL 100 138#define CLK_TOP_ATB_SEL 101 139#define CLK_TOP_CAMTG_SEL 102 140#define CLK_TOP_CAMTG1_SEL 103 141#define CLK_TOP_CAMTG2_SEL 104 142#define CLK_TOP_CAMTG3_SEL 105 143#define CLK_TOP_UART_SEL 106 144#define CLK_TOP_SPI_SEL 107 145#define CLK_TOP_MSDC50_0_HCLK_SEL 108 146#define CLK_TOP_MSDC50_0_SEL 109 147#define CLK_TOP_MSDC30_1_SEL 110 148#define CLK_TOP_AUDIO_SEL 111 149#define CLK_TOP_AUD_INTBUS_SEL 112 150#define CLK_TOP_AUD_1_SEL 113 151#define CLK_TOP_AUD_ENGEN1_SEL 114 152#define CLK_TOP_DISP_PWM_SEL 115 153#define CLK_TOP_SSPM_SEL 116 154#define CLK_TOP_DXCC_SEL 117 155#define CLK_TOP_USB_TOP_SEL 118 156#define CLK_TOP_SPM_SEL 119 157#define CLK_TOP_I2C_SEL 120 158#define CLK_TOP_PWM_SEL 121 159#define CLK_TOP_SENINF_SEL 122 160#define CLK_TOP_AES_FDE_SEL 123 161#define CLK_TOP_PWRAP_ULPOSC_SEL 124 162#define CLK_TOP_CAMTM_SEL 125 163#define CLK_TOP_NR_CLK 126 164 165/* INFRACFG */ 166#define CLK_IFR_ICUSB 0 167#define CLK_IFR_GCE 1 168#define CLK_IFR_THERM 2 169#define CLK_IFR_I2C_AP 3 170#define CLK_IFR_I2C_CCU 4 171#define CLK_IFR_I2C_SSPM 5 172#define CLK_IFR_I2C_RSV 6 173#define CLK_IFR_PWM_HCLK 7 174#define CLK_IFR_PWM1 8 175#define CLK_IFR_PWM2 9 176#define CLK_IFR_PWM3 10 177#define CLK_IFR_PWM4 11 178#define CLK_IFR_PWM5 12 179#define CLK_IFR_PWM 13 180#define CLK_IFR_UART0 14 181#define CLK_IFR_UART1 15 182#define CLK_IFR_GCE_26M 16 183#define CLK_IFR_CQ_DMA_FPC 17 184#define CLK_IFR_BTIF 18 185#define CLK_IFR_SPI0 19 186#define CLK_IFR_MSDC0 20 187#define CLK_IFR_MSDC1 21 188#define CLK_IFR_TRNG 22 189#define CLK_IFR_AUXADC 23 190#define CLK_IFR_CCIF1_AP 24 191#define CLK_IFR_CCIF1_MD 25 192#define CLK_IFR_AUXADC_MD 26 193#define CLK_IFR_AP_DMA 27 194#define CLK_IFR_DEVICE_APC 28 195#define CLK_IFR_CCIF_AP 29 196#define CLK_IFR_AUDIO 30 197#define CLK_IFR_CCIF_MD 31 198#define CLK_IFR_RG_PWM_FBCLK6 32 199#define CLK_IFR_DISP_PWM 33 200#define CLK_IFR_CLDMA_BCLK 34 201#define CLK_IFR_AUDIO_26M_BCLK 35 202#define CLK_IFR_SPI1 36 203#define CLK_IFR_I2C4 37 204#define CLK_IFR_SPI2 38 205#define CLK_IFR_SPI3 39 206#define CLK_IFR_I2C5 40 207#define CLK_IFR_I2C5_ARBITER 41 208#define CLK_IFR_I2C5_IMM 42 209#define CLK_IFR_I2C1_ARBITER 43 210#define CLK_IFR_I2C1_IMM 44 211#define CLK_IFR_I2C2_ARBITER 45 212#define CLK_IFR_I2C2_IMM 46 213#define CLK_IFR_SPI4 47 214#define CLK_IFR_SPI5 48 215#define CLK_IFR_CQ_DMA 49 216#define CLK_IFR_FAES_FDE 50 217#define CLK_IFR_MSDC0_SELF 51 218#define CLK_IFR_MSDC1_SELF 52 219#define CLK_IFR_I2C6 53 220#define CLK_IFR_AP_MSDC0 54 221#define CLK_IFR_MD_MSDC0 55 222#define CLK_IFR_MSDC0_SRC 56 223#define CLK_IFR_MSDC1_SRC 57 224#define CLK_IFR_AES_TOP0_BCLK 58 225#define CLK_IFR_MCU_PM_BCLK 59 226#define CLK_IFR_CCIF2_AP 60 227#define CLK_IFR_CCIF2_MD 61 228#define CLK_IFR_CCIF3_AP 62 229#define CLK_IFR_CCIF3_MD 63 230#define CLK_IFR_NR_CLK 64 231 232/* AUDIO */ 233#define CLK_AUDIO_AFE 0 234#define CLK_AUDIO_22M 1 235#define CLK_AUDIO_APLL_TUNER 2 236#define CLK_AUDIO_ADC 3 237#define CLK_AUDIO_DAC 4 238#define CLK_AUDIO_DAC_PREDIS 5 239#define CLK_AUDIO_TML 6 240#define CLK_AUDIO_I2S1_BCLK 7 241#define CLK_AUDIO_I2S2_BCLK 8 242#define CLK_AUDIO_I2S3_BCLK 9 243#define CLK_AUDIO_I2S4_BCLK 10 244#define CLK_AUDIO_NR_CLK 11 245 246/* MIPI_RX_ANA_CSI0A */ 247 248#define CLK_MIPI0A_CSR_CSI_EN_0A 0 249#define CLK_MIPI0A_NR_CLK 1 250 251/* MMSYS_CONFIG */ 252 253#define CLK_MM_MDP_RDMA0 0 254#define CLK_MM_MDP_CCORR0 1 255#define CLK_MM_MDP_RSZ0 2 256#define CLK_MM_MDP_RSZ1 3 257#define CLK_MM_MDP_TDSHP0 4 258#define CLK_MM_MDP_WROT0 5 259#define CLK_MM_MDP_WDMA0 6 260#define CLK_MM_DISP_OVL0 7 261#define CLK_MM_DISP_OVL0_2L 8 262#define CLK_MM_DISP_RSZ0 9 263#define CLK_MM_DISP_RDMA0 10 264#define CLK_MM_DISP_WDMA0 11 265#define CLK_MM_DISP_COLOR0 12 266#define CLK_MM_DISP_CCORR0 13 267#define CLK_MM_DISP_AAL0 14 268#define CLK_MM_DISP_GAMMA0 15 269#define CLK_MM_DISP_DITHER0 16 270#define CLK_MM_DSI0 17 271#define CLK_MM_FAKE_ENG 18 272#define CLK_MM_SMI_COMMON 19 273#define CLK_MM_SMI_LARB0 20 274#define CLK_MM_SMI_COMM0 21 275#define CLK_MM_SMI_COMM1 22 276#define CLK_MM_CAM_MDP 23 277#define CLK_MM_SMI_IMG 24 278#define CLK_MM_SMI_CAM 25 279#define CLK_MM_IMG_DL_RELAY 26 280#define CLK_MM_IMG_DL_ASYNC_TOP 27 281#define CLK_MM_DIG_DSI 28 282#define CLK_MM_F26M_HRTWT 29 283#define CLK_MM_NR_CLK 30 284 285/* IMGSYS */ 286 287#define CLK_IMG_LARB2 0 288#define CLK_IMG_DIP 1 289#define CLK_IMG_FDVT 2 290#define CLK_IMG_DPE 3 291#define CLK_IMG_RSC 4 292#define CLK_IMG_NR_CLK 5 293 294/* VENCSYS */ 295 296#define CLK_VENC_SET0_LARB 0 297#define CLK_VENC_SET1_VENC 1 298#define CLK_VENC_SET2_JPGENC 2 299#define CLK_VENC_SET3_VDEC 3 300#define CLK_VENC_NR_CLK 4 301 302/* CAMSYS */ 303 304#define CLK_CAM_LARB3 0 305#define CLK_CAM_DFP_VAD 1 306#define CLK_CAM 2 307#define CLK_CAMTG 3 308#define CLK_CAM_SENINF 4 309#define CLK_CAMSV0 5 310#define CLK_CAMSV1 6 311#define CLK_CAMSV2 7 312#define CLK_CAM_CCU 8 313#define CLK_CAM_NR_CLK 9 314 315#endif /* _DT_BINDINGS_CLK_MT6765_H */ 316