1/* $NetBSD: exynos4.h,v 1.1.1.4 2020/01/03 14:33:04 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0 */ 4/* 5 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6 * Author: Andrzej Hajda <a.hajda@samsung.com> 7 * 8 * Device Tree binding constants for Exynos4 clock controller. 9 */ 10 11#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H 12#define _DT_BINDINGS_CLOCK_EXYNOS_4_H 13 14/* core clocks */ 15#define CLK_XXTI 1 16#define CLK_XUSBXTI 2 17#define CLK_FIN_PLL 3 18#define CLK_FOUT_APLL 4 19#define CLK_FOUT_MPLL 5 20#define CLK_FOUT_EPLL 6 21#define CLK_FOUT_VPLL 7 22#define CLK_SCLK_APLL 8 23#define CLK_SCLK_MPLL 9 24#define CLK_SCLK_EPLL 10 25#define CLK_SCLK_VPLL 11 26#define CLK_ARM_CLK 12 27#define CLK_ACLK200 13 28#define CLK_ACLK100 14 29#define CLK_ACLK160 15 30#define CLK_ACLK133 16 31#define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */ 32#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ 33#define CLK_MOUT_CORE 19 34#define CLK_MOUT_APLL 20 35#define CLK_SCLK_HDMIPHY 22 36#define CLK_OUT_DMC 23 37#define CLK_OUT_TOP 24 38#define CLK_OUT_LEFTBUS 25 39#define CLK_OUT_RIGHTBUS 26 40#define CLK_OUT_CPU 27 41 42/* gate for special clocks (sclk) */ 43#define CLK_SCLK_FIMC0 128 44#define CLK_SCLK_FIMC1 129 45#define CLK_SCLK_FIMC2 130 46#define CLK_SCLK_FIMC3 131 47#define CLK_SCLK_CAM0 132 48#define CLK_SCLK_CAM1 133 49#define CLK_SCLK_CSIS0 134 50#define CLK_SCLK_CSIS1 135 51#define CLK_SCLK_HDMI 136 52#define CLK_SCLK_MIXER 137 53#define CLK_SCLK_DAC 138 54#define CLK_SCLK_PIXEL 139 55#define CLK_SCLK_FIMD0 140 56#define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */ 57#define CLK_SCLK_MDNIE_PWM0 142 58#define CLK_SCLK_MIPI0 143 59#define CLK_SCLK_AUDIO0 144 60#define CLK_SCLK_MMC0 145 61#define CLK_SCLK_MMC1 146 62#define CLK_SCLK_MMC2 147 63#define CLK_SCLK_MMC3 148 64#define CLK_SCLK_MMC4 149 65#define CLK_SCLK_SATA 150 /* Exynos4210 only */ 66#define CLK_SCLK_UART0 151 67#define CLK_SCLK_UART1 152 68#define CLK_SCLK_UART2 153 69#define CLK_SCLK_UART3 154 70#define CLK_SCLK_UART4 155 71#define CLK_SCLK_AUDIO1 156 72#define CLK_SCLK_AUDIO2 157 73#define CLK_SCLK_SPDIF 158 74#define CLK_SCLK_SPI0 159 75#define CLK_SCLK_SPI1 160 76#define CLK_SCLK_SPI2 161 77#define CLK_SCLK_SLIMBUS 162 78#define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ 79#define CLK_SCLK_MIPI1 164 /* Exynos4210 only */ 80#define CLK_SCLK_PCM1 165 81#define CLK_SCLK_PCM2 166 82#define CLK_SCLK_I2S1 167 83#define CLK_SCLK_I2S2 168 84#define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */ 85#define CLK_SCLK_MFC 170 86#define CLK_SCLK_PCM0 171 87#define CLK_SCLK_G3D 172 88#define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */ 89#define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */ 90#define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */ 91#define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */ 92#define CLK_SCLK_FIMG2D 177 93 94/* gate clocks */ 95#define CLK_SSS 255 96#define CLK_FIMC0 256 97#define CLK_FIMC1 257 98#define CLK_FIMC2 258 99#define CLK_FIMC3 259 100#define CLK_CSIS0 260 101#define CLK_CSIS1 261 102#define CLK_JPEG 262 103#define CLK_SMMU_FIMC0 263 104#define CLK_SMMU_FIMC1 264 105#define CLK_SMMU_FIMC2 265 106#define CLK_SMMU_FIMC3 266 107#define CLK_SMMU_JPEG 267 108#define CLK_VP 268 109#define CLK_MIXER 269 110#define CLK_TVENC 270 /* Exynos4210 only */ 111#define CLK_HDMI 271 112#define CLK_SMMU_TV 272 113#define CLK_MFC 273 114#define CLK_SMMU_MFCL 274 115#define CLK_SMMU_MFCR 275 116#define CLK_G3D 276 117#define CLK_G2D 277 118#define CLK_ROTATOR 278 119#define CLK_MDMA 279 120#define CLK_SMMU_G2D 280 121#define CLK_SMMU_ROTATOR 281 122#define CLK_SMMU_MDMA 282 123#define CLK_FIMD0 283 124#define CLK_MIE0 284 125#define CLK_MDNIE0 285 /* Exynos4412 only */ 126#define CLK_DSIM0 286 127#define CLK_SMMU_FIMD0 287 128#define CLK_FIMD1 288 /* Exynos4210 only */ 129#define CLK_MIE1 289 /* Exynos4210 only */ 130#define CLK_DSIM1 290 /* Exynos4210 only */ 131#define CLK_SMMU_FIMD1 291 /* Exynos4210 only */ 132#define CLK_PDMA0 292 133#define CLK_PDMA1 293 134#define CLK_PCIE_PHY 294 135#define CLK_SATA_PHY 295 /* Exynos4210 only */ 136#define CLK_TSI 296 137#define CLK_SDMMC0 297 138#define CLK_SDMMC1 298 139#define CLK_SDMMC2 299 140#define CLK_SDMMC3 300 141#define CLK_SDMMC4 301 142#define CLK_SATA 302 /* Exynos4210 only */ 143#define CLK_SROMC 303 144#define CLK_USB_HOST 304 145#define CLK_USB_DEVICE 305 146#define CLK_PCIE 306 147#define CLK_ONENAND 307 148#define CLK_NFCON 308 149#define CLK_SMMU_PCIE 309 150#define CLK_GPS 310 151#define CLK_SMMU_GPS 311 152#define CLK_UART0 312 153#define CLK_UART1 313 154#define CLK_UART2 314 155#define CLK_UART3 315 156#define CLK_UART4 316 157#define CLK_I2C0 317 158#define CLK_I2C1 318 159#define CLK_I2C2 319 160#define CLK_I2C3 320 161#define CLK_I2C4 321 162#define CLK_I2C5 322 163#define CLK_I2C6 323 164#define CLK_I2C7 324 165#define CLK_I2C_HDMI 325 166#define CLK_TSADC 326 167#define CLK_SPI0 327 168#define CLK_SPI1 328 169#define CLK_SPI2 329 170#define CLK_I2S1 330 171#define CLK_I2S2 331 172#define CLK_PCM0 332 173#define CLK_I2S0 333 174#define CLK_PCM1 334 175#define CLK_PCM2 335 176#define CLK_PWM 336 177#define CLK_SLIMBUS 337 178#define CLK_SPDIF 338 179#define CLK_AC97 339 180#define CLK_MODEMIF 340 181#define CLK_CHIPID 341 182#define CLK_SYSREG 342 183#define CLK_HDMI_CEC 343 184#define CLK_MCT 344 185#define CLK_WDT 345 186#define CLK_RTC 346 187#define CLK_KEYIF 347 188#define CLK_AUDSS 348 189#define CLK_MIPI_HSI 349 /* Exynos4210 only */ 190#define CLK_PIXELASYNCM0 351 191#define CLK_PIXELASYNCM1 352 192#define CLK_ASYNC_G3D 353 /* Exynos4x12 only */ 193#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ 194#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ 195#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ 196#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */ 197#define CLK_TMU_APBIF 383 198 199/* mux clocks */ 200#define CLK_MOUT_FIMC0 384 201#define CLK_MOUT_FIMC1 385 202#define CLK_MOUT_FIMC2 386 203#define CLK_MOUT_FIMC3 387 204#define CLK_MOUT_CAM0 388 205#define CLK_MOUT_CAM1 389 206#define CLK_MOUT_CSIS0 390 207#define CLK_MOUT_CSIS1 391 208#define CLK_MOUT_G3D0 392 209#define CLK_MOUT_G3D1 393 210#define CLK_MOUT_G3D 394 211#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ 212#define CLK_MOUT_HDMI 396 213#define CLK_MOUT_MIXER 397 214 215/* gate clocks - ppmu */ 216#define CLK_PPMULEFT 400 217#define CLK_PPMURIGHT 401 218#define CLK_PPMUCAMIF 402 219#define CLK_PPMUTV 403 220#define CLK_PPMUMFC_L 404 221#define CLK_PPMUMFC_R 405 222#define CLK_PPMUG3D 406 223#define CLK_PPMUIMAGE 407 224#define CLK_PPMULCD0 408 225#define CLK_PPMULCD1 409 /* Exynos4210 only */ 226#define CLK_PPMUFILE 410 227#define CLK_PPMUGPS 411 228#define CLK_PPMUDMC0 412 229#define CLK_PPMUDMC1 413 230#define CLK_PPMUCPU 414 231#define CLK_PPMUACP 415 232 233/* div clocks */ 234#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ 235#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ 236#define CLK_DIV_ACP 456 237#define CLK_DIV_DMC 457 238#define CLK_DIV_C2C 458 /* Exynos4x12 only */ 239#define CLK_DIV_GDL 459 240#define CLK_DIV_GDR 460 241 242/* must be greater than maximal clock id */ 243#define CLK_NR_CLKS 461 244 245/* Exynos4x12 ISP clocks */ 246#define CLK_ISP_FIMC_ISP 1 247#define CLK_ISP_FIMC_DRC 2 248#define CLK_ISP_FIMC_FD 3 249#define CLK_ISP_FIMC_LITE0 4 250#define CLK_ISP_FIMC_LITE1 5 251#define CLK_ISP_MCUISP 6 252#define CLK_ISP_GICISP 7 253#define CLK_ISP_SMMU_ISP 8 254#define CLK_ISP_SMMU_DRC 9 255#define CLK_ISP_SMMU_FD 10 256#define CLK_ISP_SMMU_LITE0 11 257#define CLK_ISP_SMMU_LITE1 12 258#define CLK_ISP_PPMUISPMX 13 259#define CLK_ISP_PPMUISPX 14 260#define CLK_ISP_MCUCTL_ISP 15 261#define CLK_ISP_MPWM_ISP 16 262#define CLK_ISP_I2C0_ISP 17 263#define CLK_ISP_I2C1_ISP 18 264#define CLK_ISP_MTCADC_ISP 19 265#define CLK_ISP_PWM_ISP 20 266#define CLK_ISP_WDT_ISP 21 267#define CLK_ISP_UART_ISP 22 268#define CLK_ISP_ASYNCAXIM 23 269#define CLK_ISP_SMMU_ISPCX 24 270#define CLK_ISP_SPI0_ISP 25 271#define CLK_ISP_SPI1_ISP 26 272 273#define CLK_ISP_DIV_ISP0 27 274#define CLK_ISP_DIV_ISP1 28 275#define CLK_ISP_DIV_MCUISP0 29 276#define CLK_ISP_DIV_MCUISP1 30 277 278#define CLK_NR_ISP_CLKS 31 279 280#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ 281