191094Sdes/* $NetBSD: bm1880-clock.h,v 1.1.1.1 2020/01/03 14:33:05 skrll Exp $ */ 292289Sdes 391094Sdes/* SPDX-License-Identifier: GPL-2.0+ */ 491094Sdes/* 591094Sdes * Device Tree binding constants for Bitmain BM1880 SoC 691094Sdes * 791094Sdes * Copyright (c) 2019 Linaro Ltd. 891094Sdes */ 991094Sdes 1091094Sdes#ifndef __DT_BINDINGS_CLOCK_BM1880_H 1191094Sdes#define __DT_BINDINGS_CLOCK_BM1880_H 1291094Sdes 1391094Sdes#define BM1880_CLK_OSC 0 1491094Sdes#define BM1880_CLK_MPLL 1 1591094Sdes#define BM1880_CLK_SPLL 2 1691094Sdes#define BM1880_CLK_FPLL 3 1791094Sdes#define BM1880_CLK_DDRPLL 4 1891094Sdes#define BM1880_CLK_A53 5 1991094Sdes#define BM1880_CLK_50M_A53 6 2091094Sdes#define BM1880_CLK_AHB_ROM 7 2191094Sdes#define BM1880_CLK_AXI_SRAM 8 2291094Sdes#define BM1880_CLK_DDR_AXI 9 2391094Sdes#define BM1880_CLK_EFUSE 10 2491094Sdes#define BM1880_CLK_APB_EFUSE 11 2591094Sdes#define BM1880_CLK_AXI5_EMMC 12 2691094Sdes#define BM1880_CLK_EMMC 13 2791094Sdes#define BM1880_CLK_100K_EMMC 14 2891094Sdes#define BM1880_CLK_AXI5_SD 15 2991094Sdes#define BM1880_CLK_SD 16 3091094Sdes#define BM1880_CLK_100K_SD 17 3191094Sdes#define BM1880_CLK_500M_ETH0 18 3291094Sdes#define BM1880_CLK_AXI4_ETH0 19 3391094Sdes#define BM1880_CLK_500M_ETH1 20 3492289Sdes#define BM1880_CLK_AXI4_ETH1 21 3591094Sdes#define BM1880_CLK_AXI1_GDMA 22 3691094Sdes#define BM1880_CLK_APB_GPIO 23 3791094Sdes#define BM1880_CLK_APB_GPIO_INTR 24 3891094Sdes#define BM1880_CLK_GPIO_DB 25 3991094Sdes#define BM1880_CLK_AXI1_MINER 26 4091094Sdes#define BM1880_CLK_AHB_SF 27 4191094Sdes#define BM1880_CLK_SDMA_AXI 28 4291094Sdes#define BM1880_CLK_SDMA_AUD 29 4391094Sdes#define BM1880_CLK_APB_I2C 30 4491094Sdes#define BM1880_CLK_APB_WDT 31 4591094Sdes#define BM1880_CLK_APB_JPEG 32 4691094Sdes#define BM1880_CLK_JPEG_AXI 33 4791094Sdes#define BM1880_CLK_AXI5_NF 34 4891094Sdes#define BM1880_CLK_APB_NF 35 4991094Sdes#define BM1880_CLK_NF 36 5091094Sdes#define BM1880_CLK_APB_PWM 37 5191094Sdes#define BM1880_CLK_DIV_0_RV 38 5291094Sdes#define BM1880_CLK_DIV_1_RV 39 5391094Sdes#define BM1880_CLK_MUX_RV 40 5491094Sdes#define BM1880_CLK_RV 41 5591094Sdes#define BM1880_CLK_APB_SPI 42 5691094Sdes#define BM1880_CLK_TPU_AXI 43 5791094Sdes#define BM1880_CLK_DIV_UART_500M 44 5891094Sdes#define BM1880_CLK_UART_500M 45 5991094Sdes#define BM1880_CLK_APB_UART 46 6091094Sdes#define BM1880_CLK_APB_I2S 47 6191094Sdes#define BM1880_CLK_AXI4_USB 48 6291094Sdes#define BM1880_CLK_APB_USB 49 6391094Sdes#define BM1880_CLK_125M_USB 50 6491094Sdes#define BM1880_CLK_33K_USB 51 6591094Sdes#define BM1880_CLK_DIV_12M_USB 52 6691094Sdes#define BM1880_CLK_12M_USB 53 6791094Sdes#define BM1880_CLK_APB_VIDEO 54 6891094Sdes#define BM1880_CLK_VIDEO_AXI 55 6991094Sdes#define BM1880_CLK_VPP_AXI 56 7091094Sdes#define BM1880_CLK_APB_VPP 57 7191094Sdes#define BM1880_CLK_DIV_0_AXI1 58 7291100Sdes#define BM1880_CLK_DIV_1_AXI1 59 7391094Sdes#define BM1880_CLK_AXI1 60 7491094Sdes#define BM1880_CLK_AXI2 61 7591100Sdes#define BM1880_CLK_AXI3 62 7691100Sdes#define BM1880_CLK_AXI4 63 7791100Sdes#define BM1880_CLK_AXI5 64 7891100Sdes#define BM1880_CLK_DIV_0_AXI6 65 7991100Sdes#define BM1880_CLK_DIV_1_AXI6 66 8091100Sdes#define BM1880_CLK_MUX_AXI6 67 8191100Sdes#define BM1880_CLK_AXI6 68 8291100Sdes#define BM1880_NR_CLKS 69 8391100Sdes 8491100Sdes#endif /* __DT_BINDINGS_CLOCK_BM1880_H */ 8591100Sdes