1/* $NetBSD: bm1880-clock.h,v 1.1.1.1 2020/01/03 14:33:05 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0+ */ 4/* 5 * Device Tree binding constants for Bitmain BM1880 SoC 6 * 7 * Copyright (c) 2019 Linaro Ltd. 8 */ 9 10#ifndef __DT_BINDINGS_CLOCK_BM1880_H 11#define __DT_BINDINGS_CLOCK_BM1880_H 12 13#define BM1880_CLK_OSC 0 14#define BM1880_CLK_MPLL 1 15#define BM1880_CLK_SPLL 2 16#define BM1880_CLK_FPLL 3 17#define BM1880_CLK_DDRPLL 4 18#define BM1880_CLK_A53 5 19#define BM1880_CLK_50M_A53 6 20#define BM1880_CLK_AHB_ROM 7 21#define BM1880_CLK_AXI_SRAM 8 22#define BM1880_CLK_DDR_AXI 9 23#define BM1880_CLK_EFUSE 10 24#define BM1880_CLK_APB_EFUSE 11 25#define BM1880_CLK_AXI5_EMMC 12 26#define BM1880_CLK_EMMC 13 27#define BM1880_CLK_100K_EMMC 14 28#define BM1880_CLK_AXI5_SD 15 29#define BM1880_CLK_SD 16 30#define BM1880_CLK_100K_SD 17 31#define BM1880_CLK_500M_ETH0 18 32#define BM1880_CLK_AXI4_ETH0 19 33#define BM1880_CLK_500M_ETH1 20 34#define BM1880_CLK_AXI4_ETH1 21 35#define BM1880_CLK_AXI1_GDMA 22 36#define BM1880_CLK_APB_GPIO 23 37#define BM1880_CLK_APB_GPIO_INTR 24 38#define BM1880_CLK_GPIO_DB 25 39#define BM1880_CLK_AXI1_MINER 26 40#define BM1880_CLK_AHB_SF 27 41#define BM1880_CLK_SDMA_AXI 28 42#define BM1880_CLK_SDMA_AUD 29 43#define BM1880_CLK_APB_I2C 30 44#define BM1880_CLK_APB_WDT 31 45#define BM1880_CLK_APB_JPEG 32 46#define BM1880_CLK_JPEG_AXI 33 47#define BM1880_CLK_AXI5_NF 34 48#define BM1880_CLK_APB_NF 35 49#define BM1880_CLK_NF 36 50#define BM1880_CLK_APB_PWM 37 51#define BM1880_CLK_DIV_0_RV 38 52#define BM1880_CLK_DIV_1_RV 39 53#define BM1880_CLK_MUX_RV 40 54#define BM1880_CLK_RV 41 55#define BM1880_CLK_APB_SPI 42 56#define BM1880_CLK_TPU_AXI 43 57#define BM1880_CLK_DIV_UART_500M 44 58#define BM1880_CLK_UART_500M 45 59#define BM1880_CLK_APB_UART 46 60#define BM1880_CLK_APB_I2S 47 61#define BM1880_CLK_AXI4_USB 48 62#define BM1880_CLK_APB_USB 49 63#define BM1880_CLK_125M_USB 50 64#define BM1880_CLK_33K_USB 51 65#define BM1880_CLK_DIV_12M_USB 52 66#define BM1880_CLK_12M_USB 53 67#define BM1880_CLK_APB_VIDEO 54 68#define BM1880_CLK_VIDEO_AXI 55 69#define BM1880_CLK_VPP_AXI 56 70#define BM1880_CLK_APB_VPP 57 71#define BM1880_CLK_DIV_0_AXI1 58 72#define BM1880_CLK_DIV_1_AXI1 59 73#define BM1880_CLK_AXI1 60 74#define BM1880_CLK_AXI2 61 75#define BM1880_CLK_AXI3 62 76#define BM1880_CLK_AXI4 63 77#define BM1880_CLK_AXI5 64 78#define BM1880_CLK_DIV_0_AXI6 65 79#define BM1880_CLK_DIV_1_AXI6 66 80#define BM1880_CLK_MUX_AXI6 67 81#define BM1880_CLK_AXI6 68 82#define BM1880_NR_CLKS 69 83 84#endif /* __DT_BINDINGS_CLOCK_BM1880_H */ 85