1/* $NetBSD: actions,s500-cmu.h,v 1.1.1.2 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0+ */ 4/* 5 * Device Tree binding constants for Actions Semi S500 Clock Management Unit 6 * 7 * Copyright (c) 2014 Actions Semi Inc. 8 * Copyright (c) 2018 LSI-TEC - Caninos Loucos 9 */ 10 11#ifndef __DT_BINDINGS_CLOCK_S500_CMU_H 12#define __DT_BINDINGS_CLOCK_S500_CMU_H 13 14#define CLK_NONE 0 15 16/* fixed rate clocks */ 17#define CLK_LOSC 1 18#define CLK_HOSC 2 19 20/* pll clocks */ 21#define CLK_CORE_PLL 3 22#define CLK_DEV_PLL 4 23#define CLK_DDR_PLL 5 24#define CLK_NAND_PLL 6 25#define CLK_DISPLAY_PLL 7 26#define CLK_ETHERNET_PLL 8 27#define CLK_AUDIO_PLL 9 28 29/* system clock */ 30#define CLK_DEV 10 31#define CLK_H 11 32#define CLK_AHBPREDIV 12 33#define CLK_AHB 13 34#define CLK_DE 14 35#define CLK_BISP 15 36#define CLK_VCE 16 37#define CLK_VDE 17 38 39/* peripheral device clock */ 40#define CLK_TIMER 18 41#define CLK_I2C0 19 42#define CLK_I2C1 20 43#define CLK_I2C2 21 44#define CLK_I2C3 22 45#define CLK_PWM0 23 46#define CLK_PWM1 24 47#define CLK_PWM2 25 48#define CLK_PWM3 26 49#define CLK_PWM4 27 50#define CLK_PWM5 28 51#define CLK_SD0 29 52#define CLK_SD1 30 53#define CLK_SD2 31 54#define CLK_SENSOR0 32 55#define CLK_SENSOR1 33 56#define CLK_SPI0 34 57#define CLK_SPI1 35 58#define CLK_SPI2 36 59#define CLK_SPI3 37 60#define CLK_UART0 38 61#define CLK_UART1 39 62#define CLK_UART2 40 63#define CLK_UART3 41 64#define CLK_UART4 42 65#define CLK_UART5 43 66#define CLK_UART6 44 67#define CLK_DE1 45 68#define CLK_DE2 46 69#define CLK_I2SRX 47 70#define CLK_I2STX 48 71#define CLK_HDMI_AUDIO 49 72#define CLK_HDMI 50 73#define CLK_SPDIF 51 74#define CLK_NAND 52 75#define CLK_ECC 53 76#define CLK_RMII_REF 54 77#define CLK_GPIO 55 78 79/* additional clocks */ 80#define CLK_APB 56 81#define CLK_DMAC 57 82#define CLK_NIC 58 83#define CLK_ETHERNET 59 84 85#define CLK_NR_CLKS (CLK_ETHERNET + 1) 86 87#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */ 88