1/*	$NetBSD$	*/
2
3#ifndef _PCI22_H
4#define _PCI22_H
5
6/*++
7
8Copyright (c) 1999  Intel Corporation
9
10Module Name:
11
12    pci22.h
13
14Abstract:
15    Support for PCI 2.2 standard.
16
17
18
19
20Revision History
21
22--*/
23
24#ifdef SOFT_SDV
25#define PCI_MAX_BUS     1
26#else
27#define PCI_MAX_BUS     255
28#endif
29
30#define PCI_MAX_DEVICE  31
31#define PCI_MAX_FUNC    7
32
33//
34// Command
35//
36#define PCI_VGA_PALETTE_SNOOP_DISABLED   0x20
37
38#pragma pack(1)
39typedef struct {
40    UINT16      VendorId;
41    UINT16      DeviceId;
42    UINT16      Command;
43    UINT16      Status;
44    UINT8       RevisionID;
45    UINT8       ClassCode[3];
46    UINT8       CacheLineSize;
47    UINT8       LaytencyTimer;
48    UINT8       HeaderType;
49    UINT8       BIST;
50} PCI_DEVICE_INDEPENDENT_REGION;
51
52typedef struct {
53    UINT32      Bar[6];
54    UINT32      CISPtr;
55    UINT16      SubsystemVendorID;
56    UINT16      SubsystemID;
57    UINT32      ExpansionRomBar;
58    UINT32      Reserved[2];
59    UINT8       InterruptLine;
60    UINT8       InterruptPin;
61    UINT8       MinGnt;
62    UINT8       MaxLat;
63} PCI_DEVICE_HEADER_TYPE_REGION;
64
65typedef struct {
66    PCI_DEVICE_INDEPENDENT_REGION   Hdr;
67    PCI_DEVICE_HEADER_TYPE_REGION   Device;
68} PCI_TYPE00;
69
70typedef struct {
71    UINT32      Bar[2];
72    UINT8       PrimaryBus;
73    UINT8       SecondaryBus;
74    UINT8       SubordinateBus;
75    UINT8       SecondaryLatencyTimer;
76    UINT8       IoBase;
77    UINT8       IoLimit;
78    UINT16      SecondaryStatus;
79    UINT16      MemoryBase;
80    UINT16      MemoryLimit;
81    UINT16      PrefetchableMemoryBase;
82    UINT16      PrefetchableMemoryLimit;
83    UINT32      PrefetchableBaseUpper32;
84    UINT32      PrefetchableLimitUpper32;
85    UINT16      IoBaseUpper16;
86    UINT16      IoLimitUpper16;
87    UINT32      Reserved;
88    UINT32      ExpansionRomBAR;
89    UINT8       InterruptLine;
90    UINT8       InterruptPin;
91    UINT16      BridgeControl;
92} PCI_BRIDGE_CONTROL_REGISTER;
93
94#define PCI_CLASS_DISPLAY_CTRL          0x03
95#define PCI_CLASS_VGA                   0x00
96
97#define PCI_CLASS_BRIDGE                0x06
98#define PCI_CLASS_ISA                   0x01
99#define PCI_CLASS_ISA_POSITIVE_DECODE   0x80
100
101#define PCI_CLASS_NETWORK               0x02
102#define PCI_CLASS_ETHERNET              0x00
103
104#define HEADER_TYPE_DEVICE              0x00
105#define HEADER_TYPE_PCI_TO_PCI_BRIDGE   0x01
106#define HEADER_TYPE_MULTI_FUNCTION      0x80
107#define HEADER_LAYOUT_CODE              0x7f
108
109#define IS_PCI_BRIDGE(_p) ((((_p)->Hdr.HeaderType) & HEADER_LAYOUT_CODE) == HEADER_TYPE_PCI_TO_PCI_BRIDGE)
110#define IS_PCI_MULTI_FUNC(_p)   (((_p)->Hdr.HeaderType) & HEADER_TYPE_MULTI_FUNCTION)
111
112typedef struct {
113    PCI_DEVICE_INDEPENDENT_REGION   Hdr;
114    PCI_BRIDGE_CONTROL_REGISTER     Bridge;
115} PCI_TYPE01;
116
117typedef struct {
118    UINT8   Register;
119    UINT8   Function;
120    UINT8   Device;
121    UINT8   Bus;
122    UINT8   Reserved[4];
123} DEFIO_PCI_ADDR;
124
125typedef struct {
126    UINT32  Reg     : 8;
127    UINT32  Func    : 3;
128    UINT32  Dev     : 5;
129    UINT32  Bus     : 8;
130    UINT32  Reserved: 7;
131    UINT32  Enable  : 1;
132} PCI_CONFIG_ACCESS_CF8;
133
134#pragma pack()
135
136#define EFI_ROOT_BRIDGE_LIST    'eprb'
137typedef struct {
138    UINTN           Signature;
139
140    UINT16          BridgeNumber;
141    UINT16          PrimaryBus;
142    UINT16          SubordinateBus;
143
144    EFI_DEVICE_PATH *DevicePath;
145
146    LIST_ENTRY      Link;
147} PCI_ROOT_BRIDGE_ENTRY;
148
149
150#define PCI_EXPANSION_ROM_HEADER_SIGNATURE        0xaa55
151#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1
152#define PCI_DATA_STRUCTURE_SIGNATURE              EFI_SIGNATURE_32('P','C','I','R')
153
154#pragma pack(1)
155typedef struct {
156    UINT16          Signature;              // 0xaa55
157    UINT8           Reserved[0x16];
158    UINT16          PcirOffset;
159} PCI_EXPANSION_ROM_HEADER;
160
161
162typedef struct {
163    UINT16          Signature;              // 0xaa55
164    UINT16          InitializationSize;
165    UINT16          EfiSignature;           // 0x0EF1
166    UINT16          EfiSubsystem;
167    UINT16          EfiMachineType;
168    UINT8           Reserved[0x0A];
169    UINT16          EfiImageHeaderOffset;
170    UINT16          PcirOffset;
171} EFI_PCI_EXPANSION_ROM_HEADER;
172
173typedef struct {
174    UINT32          Signature;              // "PCIR"
175    UINT16          VendorId;
176    UINT16          DeviceId;
177    UINT16          Reserved0;
178    UINT16          Length;
179    UINT8           Revision;
180    UINT8           ClassCode[3];
181    UINT16          ImageLength;
182    UINT16          CodeRevision;
183    UINT8           CodeType;
184    UINT8           Indicator;
185    UINT16          Reserved1;
186} PCI_DATA_STRUCTURE;
187#pragma pack()
188
189#endif
190
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