1/*	$NetBSD: rs780_dpm.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $	*/
2
3/*
4 * Copyright 2011 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25#ifndef __RS780_DPM_H__
26#define __RS780_DPM_H__
27
28enum rs780_vddc_level {
29	RS780_VDDC_LEVEL_UNKNOWN = 0,
30	RS780_VDDC_LEVEL_LOW = 1,
31	RS780_VDDC_LEVEL_HIGH = 2,
32};
33
34struct igp_power_info {
35	/* flags */
36	bool invert_pwm_required;
37	bool pwm_voltage_control;
38	bool voltage_control;
39	bool gfx_clock_gating;
40	/* stored values */
41	u32 system_config;
42	u32 bootup_uma_clk;
43	u16 max_voltage;
44	u16 min_voltage;
45	u16 boot_voltage;
46	u16 inter_voltage_low;
47	u16 inter_voltage_high;
48	u16 num_of_cycles_in_period;
49	/* variable */
50	int crtc_id;
51	int refresh_rate;
52};
53
54struct igp_ps {
55	enum rs780_vddc_level min_voltage;
56	enum rs780_vddc_level max_voltage;
57	u32 sclk_low;
58	u32 sclk_high;
59	u32 flags;
60};
61
62#define RS780_CGFTV_DFLT                 0x0303000f
63#define RS780_FBDIVTIMERVAL_DFLT         0x2710
64
65#define RS780_FVTHROTUTC0_DFLT   0x04010040
66#define RS780_FVTHROTUTC1_DFLT   0x04010040
67#define RS780_FVTHROTUTC2_DFLT   0x04010040
68#define RS780_FVTHROTUTC3_DFLT   0x04010040
69#define RS780_FVTHROTUTC4_DFLT   0x04010040
70
71#define RS780_FVTHROTDTC0_DFLT 0x04010040
72#define RS780_FVTHROTDTC1_DFLT 0x04010040
73#define RS780_FVTHROTDTC2_DFLT 0x04010040
74#define RS780_FVTHROTDTC3_DFLT 0x04010040
75#define RS780_FVTHROTDTC4_DFLT 0x04010040
76
77#define RS780_FVTHROTFBUSREG0_DFLT       0x00001001
78#define RS780_FVTHROTFBUSREG1_DFLT       0x00002002
79#define RS780_FVTHROTFBDSREG0_DFLT       0x00004001
80#define RS780_FVTHROTFBDSREG1_DFLT       0x00020010
81
82#define RS780_FVTHROTPWMUSREG0_DFLT      0x00002001
83#define RS780_FVTHROTPWMUSREG1_DFLT      0x00004003
84#define RS780_FVTHROTPWMDSREG0_DFLT      0x00002001
85#define RS780_FVTHROTPWMDSREG1_DFLT      0x00004003
86
87#define RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT  0x37
88#define RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT  0x4b
89#define RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT  0x8b
90
91#define RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT  0x8b
92#define RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT  0x8c
93#define RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT  0xb5
94
95#define RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT  0x8d
96#define RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT  0x8e
97#define RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT  0xBa
98
99#define RS780_FVTHROTPWMRANGE0_GPIO_DFLT  0x1a
100#define RS780_FVTHROTPWMRANGE1_GPIO_DFLT  0x1a
101#define RS780_FVTHROTPWMRANGE2_GPIO_DFLT  0x0
102#define RS780_FVTHROTPWMRANGE3_GPIO_DFLT  0x0
103
104#define RS780_SLOWCLKFEEDBACKDIV_DFLT 110
105
106#define RS780_CGCLKGATING_DFLT           0x0000E204
107
108#define RS780_DEFAULT_VCLK_FREQ  53300 /* 10 khz */
109#define RS780_DEFAULT_DCLK_FREQ  40000 /* 10 khz */
110
111#endif
112