1/* $NetBSD: radeon_mode.h,v 1.8 2021/12/19 10:38:05 riastradh Exp $ */ 2 3/* 4 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 5 * VA Linux Systems Inc., Fremont, California. 6 * Copyright 2008 Red Hat Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Original Authors: 27 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 28 * 29 * Kernel port Author: Dave Airlie 30 */ 31 32#ifndef RADEON_MODE_H 33#define RADEON_MODE_H 34 35#include <drm/drm_crtc.h> 36#include <drm/drm_edid.h> 37#include <drm/drm_encoder.h> 38#include <drm/drm_dp_helper.h> 39#include <drm/drm_dp_mst_helper.h> 40#include <drm/drm_fixed.h> 41#include <drm/drm_crtc_helper.h> 42#include <linux/i2c.h> 43#include <linux/i2c-algo-bit.h> 44 45struct radeon_bo; 46struct radeon_device; 47 48#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 49#define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 50#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 51 52#define RADEON_MAX_HPD_PINS 7 53#define RADEON_MAX_CRTCS 6 54#define RADEON_MAX_AFMT_BLOCKS 7 55 56enum radeon_rmx_type { 57 RMX_OFF, 58 RMX_FULL, 59 RMX_CENTER, 60 RMX_ASPECT 61}; 62 63enum radeon_tv_std { 64 TV_STD_NTSC, 65 TV_STD_PAL, 66 TV_STD_PAL_M, 67 TV_STD_PAL_60, 68 TV_STD_NTSC_J, 69 TV_STD_SCART_PAL, 70 TV_STD_SECAM, 71 TV_STD_PAL_CN, 72 TV_STD_PAL_N, 73}; 74 75enum radeon_underscan_type { 76 UNDERSCAN_OFF, 77 UNDERSCAN_ON, 78 UNDERSCAN_AUTO, 79}; 80 81enum radeon_hpd_id { 82 RADEON_HPD_1 = 0, 83 RADEON_HPD_2, 84 RADEON_HPD_3, 85 RADEON_HPD_4, 86 RADEON_HPD_5, 87 RADEON_HPD_6, 88 RADEON_HPD_NONE = 0xff, 89}; 90 91enum radeon_output_csc { 92 RADEON_OUTPUT_CSC_BYPASS = 0, 93 RADEON_OUTPUT_CSC_TVRGB = 1, 94 RADEON_OUTPUT_CSC_YCBCR601 = 2, 95 RADEON_OUTPUT_CSC_YCBCR709 = 3, 96}; 97 98#define RADEON_MAX_I2C_BUS 16 99 100/* radeon gpio-based i2c 101 * 1. "mask" reg and bits 102 * grabs the gpio pins for software use 103 * 0=not held 1=held 104 * 2. "a" reg and bits 105 * output pin value 106 * 0=low 1=high 107 * 3. "en" reg and bits 108 * sets the pin direction 109 * 0=input 1=output 110 * 4. "y" reg and bits 111 * input pin value 112 * 0=low 1=high 113 */ 114struct radeon_i2c_bus_rec { 115 bool valid; 116 /* id used by atom */ 117 uint8_t i2c_id; 118 /* id used by atom */ 119 enum radeon_hpd_id hpd; 120 /* can be used with hw i2c engine */ 121 bool hw_capable; 122 /* uses multi-media i2c engine */ 123 bool mm_i2c; 124 /* regs and bits */ 125 uint32_t mask_clk_reg; 126 uint32_t mask_data_reg; 127 uint32_t a_clk_reg; 128 uint32_t a_data_reg; 129 uint32_t en_clk_reg; 130 uint32_t en_data_reg; 131 uint32_t y_clk_reg; 132 uint32_t y_data_reg; 133 uint32_t mask_clk_mask; 134 uint32_t mask_data_mask; 135 uint32_t a_clk_mask; 136 uint32_t a_data_mask; 137 uint32_t en_clk_mask; 138 uint32_t en_data_mask; 139 uint32_t y_clk_mask; 140 uint32_t y_data_mask; 141}; 142 143struct radeon_tmds_pll { 144 uint32_t freq; 145 uint32_t value; 146}; 147 148#define RADEON_MAX_BIOS_CONNECTOR 16 149 150/* pll flags */ 151#define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 152#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 153#define RADEON_PLL_USE_REF_DIV (1 << 2) 154#define RADEON_PLL_LEGACY (1 << 3) 155#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 156#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 157#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 158#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 159#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 160#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 161#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 162#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 163#define RADEON_PLL_USE_POST_DIV (1 << 12) 164#define RADEON_PLL_IS_LCD (1 << 13) 165#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 166 167struct radeon_pll { 168 /* reference frequency */ 169 uint32_t reference_freq; 170 171 /* fixed dividers */ 172 uint32_t reference_div; 173 uint32_t post_div; 174 175 /* pll in/out limits */ 176 uint32_t pll_in_min; 177 uint32_t pll_in_max; 178 uint32_t pll_out_min; 179 uint32_t pll_out_max; 180 uint32_t lcd_pll_out_min; 181 uint32_t lcd_pll_out_max; 182 uint32_t best_vco; 183 184 /* divider limits */ 185 uint32_t min_ref_div; 186 uint32_t max_ref_div; 187 uint32_t min_post_div; 188 uint32_t max_post_div; 189 uint32_t min_feedback_div; 190 uint32_t max_feedback_div; 191 uint32_t min_frac_feedback_div; 192 uint32_t max_frac_feedback_div; 193 194 /* flags for the current clock */ 195 uint32_t flags; 196 197 /* pll id */ 198 uint32_t id; 199}; 200 201struct radeon_i2c_chan { 202 struct i2c_adapter adapter; 203 struct drm_device *dev; 204 struct i2c_algo_bit_data bit; 205 struct radeon_i2c_bus_rec rec; 206 struct drm_dp_aux aux; 207 bool has_aux; 208 struct mutex mutex; 209}; 210 211/* mostly for macs, but really any system without connector tables */ 212enum radeon_connector_table { 213 CT_NONE = 0, 214 CT_GENERIC, 215 CT_IBOOK, 216 CT_POWERBOOK_EXTERNAL, 217 CT_POWERBOOK_INTERNAL, 218 CT_POWERBOOK_VGA, 219 CT_MINI_EXTERNAL, 220 CT_MINI_INTERNAL, 221 CT_IMAC_G5_ISIGHT, 222 CT_EMAC, 223 CT_RN50_POWER, 224 CT_MAC_X800, 225 CT_MAC_G5_9600, 226 CT_SAM440EP, 227 CT_MAC_G4_SILVER 228}; 229 230enum radeon_dvo_chip { 231 DVO_SIL164, 232 DVO_SIL1178, 233}; 234 235struct radeon_fbdev; 236 237struct radeon_afmt { 238 bool enabled; 239 int offset; 240 bool last_buffer_filled_status; 241 int id; 242}; 243 244struct radeon_mode_info { 245 struct atom_context *atom_context; 246 struct card_info *atom_card_info; 247 enum radeon_connector_table connector_table; 248 bool mode_config_initialized; 249 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; 250 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; 251 /* DVI-I properties */ 252 struct drm_property *coherent_mode_property; 253 /* DAC enable load detect */ 254 struct drm_property *load_detect_property; 255 /* TV standard */ 256 struct drm_property *tv_std_property; 257 /* legacy TMDS PLL detect */ 258 struct drm_property *tmds_pll_property; 259 /* underscan */ 260 struct drm_property *underscan_property; 261 struct drm_property *underscan_hborder_property; 262 struct drm_property *underscan_vborder_property; 263 /* audio */ 264 struct drm_property *audio_property; 265 /* FMT dithering */ 266 struct drm_property *dither_property; 267 /* Output CSC */ 268 struct drm_property *output_csc_property; 269 /* hardcoded DFP edid from BIOS */ 270 struct edid *bios_hardcoded_edid; 271 int bios_hardcoded_edid_size; 272 273 /* pointer to fbdev info structure */ 274 struct radeon_fbdev *rfbdev; 275 /* firmware flags */ 276 u16 firmware_flags; 277 /* pointer to backlight encoder */ 278 struct radeon_encoder *bl_encoder; 279 280 /* bitmask for active encoder frontends */ 281 uint32_t active_encoders; 282}; 283 284#define RADEON_MAX_BL_LEVEL 0xFF 285 286#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 287 288struct radeon_backlight_privdata { 289 struct radeon_encoder *encoder; 290 uint8_t negative; 291}; 292 293#endif 294 295#define MAX_H_CODE_TIMING_LEN 32 296#define MAX_V_CODE_TIMING_LEN 32 297 298/* need to store these as reading 299 back code tables is excessive */ 300struct radeon_tv_regs { 301 uint32_t tv_uv_adr; 302 uint32_t timing_cntl; 303 uint32_t hrestart; 304 uint32_t vrestart; 305 uint32_t frestart; 306 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 307 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 308}; 309 310struct radeon_atom_ss { 311 uint16_t percentage; 312 uint16_t percentage_divider; 313 uint8_t type; 314 uint16_t step; 315 uint8_t delay; 316 uint8_t range; 317 uint8_t refdiv; 318 /* asic_ss */ 319 uint16_t rate; 320 uint16_t amount; 321}; 322 323enum radeon_flip_status { 324 RADEON_FLIP_NONE, 325 RADEON_FLIP_PENDING, 326 RADEON_FLIP_SUBMITTED 327}; 328 329struct radeon_crtc { 330 struct drm_crtc base; 331 int crtc_id; 332 bool enabled; 333 bool can_tile; 334 bool cursor_out_of_bounds; 335 uint32_t crtc_offset; 336 struct drm_gem_object *cursor_bo; 337 uint64_t cursor_addr; 338 int cursor_x; 339 int cursor_y; 340 int cursor_hot_x; 341 int cursor_hot_y; 342 int cursor_width; 343 int cursor_height; 344 int max_cursor_width; 345 int max_cursor_height; 346 uint32_t legacy_display_base_addr; 347 enum radeon_rmx_type rmx_type; 348 u8 h_border; 349 u8 v_border; 350 fixed20_12 vsc; 351 fixed20_12 hsc; 352 struct drm_display_mode native_mode; 353 int pll_id; 354 /* page flipping */ 355 struct workqueue_struct *flip_queue; 356 struct radeon_flip_work *flip_work; 357 enum radeon_flip_status flip_status; 358 /* pll sharing */ 359 struct radeon_atom_ss ss; 360 bool ss_enabled; 361 u32 adjusted_clock; 362 int bpc; 363 u32 pll_reference_div; 364 u32 pll_post_div; 365 u32 pll_flags; 366 struct drm_encoder *encoder; 367 struct drm_connector *connector; 368 /* for dpm */ 369 u32 line_time; 370 u32 wm_low; 371 u32 wm_high; 372 u32 lb_vblank_lead_lines; 373 struct drm_display_mode hw_mode; 374 enum radeon_output_csc output_csc; 375}; 376 377struct radeon_encoder_primary_dac { 378 /* legacy primary dac */ 379 uint32_t ps2_pdac_adj; 380}; 381 382struct radeon_encoder_lvds { 383 /* legacy lvds */ 384 uint16_t panel_vcc_delay; 385 uint8_t panel_pwr_delay; 386 uint8_t panel_digon_delay; 387 uint8_t panel_blon_delay; 388 uint16_t panel_ref_divider; 389 uint8_t panel_post_divider; 390 uint16_t panel_fb_divider; 391 bool use_bios_dividers; 392 uint32_t lvds_gen_cntl; 393 /* panel mode */ 394 struct drm_display_mode native_mode; 395 struct backlight_device *bl_dev; 396 int dpms_mode; 397 uint8_t backlight_level; 398}; 399 400struct radeon_encoder_tv_dac { 401 /* legacy tv dac */ 402 uint32_t ps2_tvdac_adj; 403 uint32_t ntsc_tvdac_adj; 404 uint32_t pal_tvdac_adj; 405 406 int h_pos; 407 int v_pos; 408 int h_size; 409 int supported_tv_stds; 410 bool tv_on; 411 enum radeon_tv_std tv_std; 412 struct radeon_tv_regs tv; 413}; 414 415struct radeon_encoder_int_tmds { 416 /* legacy int tmds */ 417 struct radeon_tmds_pll tmds_pll[4]; 418}; 419 420struct radeon_encoder_ext_tmds { 421 /* tmds over dvo */ 422 struct radeon_i2c_chan *i2c_bus; 423 uint8_t slave_addr; 424 enum radeon_dvo_chip dvo_chip; 425}; 426 427/* spread spectrum */ 428struct radeon_encoder_atom_dig { 429 bool linkb; 430 /* atom dig */ 431 bool coherent_mode; 432 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 433 /* atom lvds/edp */ 434 uint32_t lcd_misc; 435 uint16_t panel_pwr_delay; 436 uint32_t lcd_ss_id; 437 /* panel mode */ 438 struct drm_display_mode native_mode; 439 struct backlight_device *bl_dev; 440 int dpms_mode; 441 uint8_t backlight_level; 442 int panel_mode; 443 struct radeon_afmt *afmt; 444 struct r600_audio_pin *pin; 445 int active_mst_links; 446}; 447 448struct radeon_encoder_atom_dac { 449 enum radeon_tv_std tv_std; 450}; 451 452struct radeon_encoder_mst { 453 int crtc; 454 struct radeon_encoder *primary; 455 struct radeon_connector *connector; 456 struct drm_dp_mst_port *port; 457 int pbn; 458 int fe; 459 bool fe_from_be; 460 bool enc_active; 461}; 462 463struct radeon_encoder { 464 struct drm_encoder base; 465 uint32_t encoder_enum; 466 uint32_t encoder_id; 467 uint32_t devices; 468 uint32_t active_device; 469 uint32_t flags; 470 uint32_t pixel_clock; 471 enum radeon_rmx_type rmx_type; 472 enum radeon_underscan_type underscan_type; 473 uint32_t underscan_hborder; 474 uint32_t underscan_vborder; 475 struct drm_display_mode native_mode; 476 void *enc_priv; 477 int audio_polling_active; 478 bool is_ext_encoder; 479 u16 caps; 480 struct radeon_audio_funcs *audio; 481 enum radeon_output_csc output_csc; 482 bool can_mst; 483 uint32_t offset; 484 bool is_mst_encoder; 485 /* front end for this mst encoder */ 486}; 487 488struct radeon_connector_atom_dig { 489 uint32_t igp_lane_info; 490 /* displayport */ 491 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 492 u8 dp_sink_type; 493 int dp_clock; 494 int dp_lane_count; 495 bool edp_on; 496 bool is_mst; 497}; 498 499struct radeon_gpio_rec { 500 bool valid; 501 u8 id; 502 u32 reg; 503 u32 mask; 504 u32 shift; 505}; 506 507struct radeon_hpd { 508 enum radeon_hpd_id hpd; 509 u8 plugged_state; 510 struct radeon_gpio_rec gpio; 511}; 512 513struct radeon_router { 514 u32 router_id; 515 struct radeon_i2c_bus_rec i2c_info; 516 u8 i2c_addr; 517 /* i2c mux */ 518 bool ddc_valid; 519 u8 ddc_mux_type; 520 u8 ddc_mux_control_pin; 521 u8 ddc_mux_state; 522 /* clock/data mux */ 523 bool cd_valid; 524 u8 cd_mux_type; 525 u8 cd_mux_control_pin; 526 u8 cd_mux_state; 527}; 528 529enum radeon_connector_audio { 530 RADEON_AUDIO_DISABLE = 0, 531 RADEON_AUDIO_ENABLE = 1, 532 RADEON_AUDIO_AUTO = 2 533}; 534 535enum radeon_connector_dither { 536 RADEON_FMT_DITHER_DISABLE = 0, 537 RADEON_FMT_DITHER_ENABLE = 1, 538}; 539 540struct stream_attribs { 541 uint16_t fe; 542 uint16_t slots; 543}; 544 545struct radeon_connector { 546 struct drm_connector base; 547 uint32_t connector_id; 548 uint32_t devices; 549 struct radeon_i2c_chan *ddc_bus; 550 /* some systems have an hdmi and vga port with a shared ddc line */ 551 bool shared_ddc; 552 bool use_digital; 553 /* we need to mind the EDID between detect 554 and get modes due to analog/digital/tvencoder */ 555 struct edid *edid; 556 void *con_priv; 557 bool dac_load_detect; 558 bool detected_by_load; /* if the connection status was determined by load */ 559 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ 560 uint16_t connector_object_id; 561 struct radeon_hpd hpd; 562 struct radeon_router router; 563 struct radeon_i2c_chan *router_bus; 564 enum radeon_connector_audio audio; 565 enum radeon_connector_dither dither; 566 int pixelclock_for_modeset; 567 bool is_mst_connector; 568 struct radeon_connector *mst_port; 569 struct drm_dp_mst_port *port; 570 struct drm_dp_mst_topology_mgr mst_mgr; 571 572 struct radeon_encoder *mst_encoder; 573 struct stream_attribs cur_stream_attribs[6]; 574 int enabled_attribs; 575}; 576 577#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 578 ((em) == ATOM_ENCODER_MODE_DP_MST)) 579 580struct atom_clock_dividers { 581 u32 post_div; 582 union { 583 struct { 584#ifdef __BIG_ENDIAN 585 u32 reserved : 6; 586 u32 whole_fb_div : 12; 587 u32 frac_fb_div : 14; 588#else 589 u32 frac_fb_div : 14; 590 u32 whole_fb_div : 12; 591 u32 reserved : 6; 592#endif 593 }; 594 u32 fb_div; 595 }; 596 u32 ref_div; 597 bool enable_post_div; 598 bool enable_dithen; 599 u32 vco_mode; 600 u32 real_clock; 601 /* added for CI */ 602 u32 post_divider; 603 u32 flags; 604}; 605 606struct atom_mpll_param { 607 union { 608 struct { 609#ifdef __BIG_ENDIAN 610 u32 reserved : 8; 611 u32 clkfrac : 12; 612 u32 clkf : 12; 613#else 614 u32 clkf : 12; 615 u32 clkfrac : 12; 616 u32 reserved : 8; 617#endif 618 }; 619 u32 fb_div; 620 }; 621 u32 post_div; 622 u32 bwcntl; 623 u32 dll_speed; 624 u32 vco_mode; 625 u32 yclk_sel; 626 u32 qdr; 627 u32 half_rate; 628}; 629 630#define MEM_TYPE_GDDR5 0x50 631#define MEM_TYPE_GDDR4 0x40 632#define MEM_TYPE_GDDR3 0x30 633#define MEM_TYPE_DDR2 0x20 634#define MEM_TYPE_GDDR1 0x10 635#define MEM_TYPE_DDR3 0xb0 636#define MEM_TYPE_MASK 0xf0 637 638struct atom_memory_info { 639 u8 mem_vendor; 640 u8 mem_type; 641}; 642 643#define MAX_AC_TIMING_ENTRIES 16 644 645struct atom_memory_clock_range_table 646{ 647 u8 num_entries; 648 u8 rsv[3]; 649 u32 mclk[MAX_AC_TIMING_ENTRIES]; 650}; 651 652#define VBIOS_MC_REGISTER_ARRAY_SIZE 32 653#define VBIOS_MAX_AC_TIMING_ENTRIES 20 654 655struct atom_mc_reg_entry { 656 u32 mclk_max; 657 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 658}; 659 660struct atom_mc_register_address { 661 u16 s1; 662 u8 pre_reg_data; 663}; 664 665struct atom_mc_reg_table { 666 u8 last; 667 u8 num_entries; 668 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 669 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 670}; 671 672#define MAX_VOLTAGE_ENTRIES 32 673 674struct atom_voltage_table_entry 675{ 676 u16 value; 677 u32 smio_low; 678}; 679 680struct atom_voltage_table 681{ 682 u32 count; 683 u32 mask_low; 684 u32 phase_delay; 685 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 686}; 687 688/* Driver internal use only flags of radeon_get_crtc_scanoutpos() */ 689#define DRM_SCANOUTPOS_VALID (1 << 0) 690#define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 691#define DRM_SCANOUTPOS_ACCURATE (1 << 2) 692#define USE_REAL_VBLANKSTART (1 << 30) 693#define GET_DISTANCE_TO_VBLANKSTART (1U << 31) 694 695extern void 696radeon_add_atom_connector(struct drm_device *dev, 697 uint32_t connector_id, 698 uint32_t supported_device, 699 int connector_type, 700 struct radeon_i2c_bus_rec *i2c_bus, 701 uint32_t igp_lane_info, 702 uint16_t connector_object_id, 703 struct radeon_hpd *hpd, 704 struct radeon_router *router); 705extern void 706radeon_add_legacy_connector(struct drm_device *dev, 707 uint32_t connector_id, 708 uint32_t supported_device, 709 int connector_type, 710 struct radeon_i2c_bus_rec *i2c_bus, 711 uint16_t connector_object_id, 712 struct radeon_hpd *hpd); 713extern uint32_t 714radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 715 uint8_t dac); 716extern void radeon_link_encoder_connector(struct drm_device *dev); 717 718extern enum radeon_tv_std 719radeon_combios_get_tv_info(struct radeon_device *rdev); 720extern enum radeon_tv_std 721radeon_atombios_get_tv_info(struct radeon_device *rdev); 722extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 723 u16 *vddc, u16 *vddci, u16 *mvdd); 724 725extern void 726radeon_combios_connected_scratch_regs(struct drm_connector *connector, 727 struct drm_encoder *encoder, 728 bool connected); 729extern void 730radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 731 struct drm_encoder *encoder, 732 bool connected); 733 734extern struct drm_connector * 735radeon_get_connector_for_encoder(struct drm_encoder *encoder); 736extern struct drm_connector * 737radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 738extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 739 u32 pixel_clock); 740 741extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 742extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 743extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 744extern int radeon_get_monitor_bpc(struct drm_connector *connector); 745 746extern struct edid *radeon_connector_edid(struct drm_connector *connector); 747 748extern void radeon_connector_hotplug(struct drm_connector *connector); 749extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 750 struct drm_display_mode *mode); 751extern void radeon_dp_set_link_config(struct drm_connector *connector, 752 const struct drm_display_mode *mode); 753extern void radeon_dp_link_train(struct drm_encoder *encoder, 754 struct drm_connector *connector); 755extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 756extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 757extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 758extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 759 struct drm_connector *connector); 760extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, 761 u8 power_state); 762extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); 763extern ssize_t 764radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); 765 766extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 767extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override); 768extern void radeon_atom_encoder_init(struct radeon_device *rdev); 769extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 770extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 771 int action, uint8_t lane_num, 772 uint8_t lane_set); 773extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, 774 int action, uint8_t lane_num, 775 uint8_t lane_set, int fe); 776extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, 777 int fe); 778extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 779extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 780void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 781 782extern void radeon_i2c_init(struct radeon_device *rdev); 783extern void radeon_i2c_fini(struct radeon_device *rdev); 784extern void radeon_combios_i2c_init(struct radeon_device *rdev); 785extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 786extern void radeon_i2c_add(struct radeon_device *rdev, 787 struct radeon_i2c_bus_rec *rec, 788 const char *name); 789extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 790 struct radeon_i2c_bus_rec *i2c_bus); 791extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 792 struct radeon_i2c_bus_rec *rec, 793 const char *name); 794extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 795extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 796 u8 slave_addr, 797 u8 addr, 798 u8 *val); 799extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 800 u8 slave_addr, 801 u8 addr, 802 u8 val); 803extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 804extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 805extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 806 807extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 808 struct radeon_atom_ss *ss, 809 int id); 810extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 811 struct radeon_atom_ss *ss, 812 int id, u32 clock); 813extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 814 u8 id); 815 816extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 817 uint64_t freq, 818 uint32_t *dot_clock_p, 819 uint32_t *fb_div_p, 820 uint32_t *frac_fb_div_p, 821 uint32_t *ref_div_p, 822 uint32_t *post_div_p); 823 824extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 825 u32 freq, 826 u32 *dot_clock_p, 827 u32 *fb_div_p, 828 u32 *frac_fb_div_p, 829 u32 *ref_div_p, 830 u32 *post_div_p); 831 832extern void radeon_setup_encoder_clones(struct drm_device *dev); 833 834struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 835struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 836struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 837struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 838struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 839extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 840extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 841extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 842extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 843extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 844extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); 845 846extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 847extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 848 struct drm_framebuffer *old_fb); 849extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 850 struct drm_framebuffer *fb, 851 int x, int y, 852 enum mode_set_atomic state); 853extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 854 struct drm_display_mode *mode, 855 struct drm_display_mode *adjusted_mode, 856 int x, int y, 857 struct drm_framebuffer *old_fb); 858extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 859 860extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 861 struct drm_framebuffer *old_fb); 862extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 863 struct drm_framebuffer *fb, 864 int x, int y, 865 enum mode_set_atomic state); 866extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 867 struct drm_framebuffer *fb, 868 int x, int y, int atomic); 869extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 870 struct drm_file *file_priv, 871 uint32_t handle, 872 uint32_t width, 873 uint32_t height, 874 int32_t hot_x, 875 int32_t hot_y); 876extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 877 int x, int y); 878extern void radeon_cursor_reset(struct drm_crtc *crtc); 879 880extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 881 unsigned int flags, int *vpos, int *hpos, 882 ktime_t *stime, ktime_t *etime, 883 const struct drm_display_mode *mode); 884 885extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 886extern struct edid * 887radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 888extern bool radeon_atom_get_clock_info(struct drm_device *dev); 889extern bool radeon_combios_get_clock_info(struct drm_device *dev); 890extern struct radeon_encoder_atom_dig * 891radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 892extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 893 struct radeon_encoder_int_tmds *tmds); 894extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 895 struct radeon_encoder_int_tmds *tmds); 896extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 897 struct radeon_encoder_int_tmds *tmds); 898extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 899 struct radeon_encoder_ext_tmds *tmds); 900extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 901 struct radeon_encoder_ext_tmds *tmds); 902extern struct radeon_encoder_primary_dac * 903radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 904extern struct radeon_encoder_tv_dac * 905radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 906extern struct radeon_encoder_lvds * 907radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 908extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 909extern struct radeon_encoder_tv_dac * 910radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 911extern struct radeon_encoder_primary_dac * 912radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 913extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 914extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 915extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 916extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 917extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 918extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 919extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 920extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 921extern void 922radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 923extern void 924radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 925extern void 926radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 927extern void 928radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 929int radeon_framebuffer_init(struct drm_device *dev, 930 struct drm_framebuffer *rfb, 931 const struct drm_mode_fb_cmd2 *mode_cmd, 932 struct drm_gem_object *obj); 933 934int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 935bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 936bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 937void radeon_atombios_init_crtc(struct drm_device *dev, 938 struct radeon_crtc *radeon_crtc); 939void radeon_legacy_init_crtc(struct drm_device *dev, 940 struct radeon_crtc *radeon_crtc); 941 942void radeon_get_clock_info(struct drm_device *dev); 943 944extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 945extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 946 947void radeon_enc_destroy(struct drm_encoder *encoder); 948void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 949void radeon_combios_asic_init(struct drm_device *dev); 950bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 951 const struct drm_display_mode *mode, 952 struct drm_display_mode *adjusted_mode); 953void radeon_panel_mode_fixup(struct drm_encoder *encoder, 954 struct drm_display_mode *adjusted_mode); 955void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 956 957/* legacy tv */ 958void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 959 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 960 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 961void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 962 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 963 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 964void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 965 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 966 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 967void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 968 struct drm_display_mode *mode, 969 struct drm_display_mode *adjusted_mode); 970 971/* fmt blocks */ 972void avivo_program_fmt(struct drm_encoder *encoder); 973void dce3_program_fmt(struct drm_encoder *encoder); 974void dce4_program_fmt(struct drm_encoder *encoder); 975void dce8_program_fmt(struct drm_encoder *encoder); 976 977/* fbdev layer */ 978int radeon_fbdev_init(struct radeon_device *rdev); 979void radeon_fbdev_fini(struct radeon_device *rdev); 980void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 981bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 982 983void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); 984 985void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector); 986void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector); 987 988void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 989 990int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 991 992/* mst */ 993int radeon_dp_mst_init(struct radeon_connector *radeon_connector); 994int radeon_dp_mst_probe(struct radeon_connector *radeon_connector); 995int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector); 996int radeon_mst_debugfs_init(struct radeon_device *rdev); 997void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode); 998 999void radeon_setup_mst_connector(struct drm_device *dev); 1000 1001int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); 1002void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); 1003#endif 1004