1/*	$NetBSD: radeon_cayman_blit_shaders.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $	*/
2
3/*
4 * Copyright 2010 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 *     Alex Deucher <alexander.deucher@amd.com>
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: radeon_cayman_blit_shaders.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $");
31
32#include <linux/bug.h>
33#include <linux/types.h>
34#include <linux/kernel.h>
35
36/*
37 * evergreen cards need to use the 3D engine to blit data which requires
38 * quite a bit of hw state setup.  Rather than pull the whole 3D driver
39 * (which normally generates the 3D state) into the DRM, we opt to use
40 * statically generated state tables.  The register state and shaders
41 * were hand generated to support blitting functionality.  See the 3D
42 * driver or documentation for descriptions of the registers and
43 * shader instructions.
44 */
45
46const u32 cayman_default_state[] =
47{
48	0xc0066900,
49	0x00000000,
50	0x00000060, /* DB_RENDER_CONTROL */
51	0x00000000, /* DB_COUNT_CONTROL */
52	0x00000000, /* DB_DEPTH_VIEW */
53	0x0000002a, /* DB_RENDER_OVERRIDE */
54	0x00000000, /* DB_RENDER_OVERRIDE2 */
55	0x00000000, /* DB_HTILE_DATA_BASE */
56
57	0xc0026900,
58	0x0000000a,
59	0x00000000, /* DB_STENCIL_CLEAR */
60	0x00000000, /* DB_DEPTH_CLEAR */
61
62	0xc0036900,
63	0x0000000f,
64	0x00000000, /* DB_DEPTH_INFO */
65	0x00000000, /* DB_Z_INFO */
66	0x00000000, /* DB_STENCIL_INFO */
67
68	0xc0016900,
69	0x00000080,
70	0x00000000, /* PA_SC_WINDOW_OFFSET */
71
72	0xc00d6900,
73	0x00000083,
74	0x0000ffff, /* PA_SC_CLIPRECT_RULE */
75	0x00000000, /* PA_SC_CLIPRECT_0_TL */
76	0x20002000, /* PA_SC_CLIPRECT_0_BR */
77	0x00000000,
78	0x20002000,
79	0x00000000,
80	0x20002000,
81	0x00000000,
82	0x20002000,
83	0xaaaaaaaa, /* PA_SC_EDGERULE */
84	0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
85	0x0000000f, /* CB_TARGET_MASK */
86	0x0000000f, /* CB_SHADER_MASK */
87
88	0xc0226900,
89	0x00000094,
90	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
91	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
92	0x80000000,
93	0x20002000,
94	0x80000000,
95	0x20002000,
96	0x80000000,
97	0x20002000,
98	0x80000000,
99	0x20002000,
100	0x80000000,
101	0x20002000,
102	0x80000000,
103	0x20002000,
104	0x80000000,
105	0x20002000,
106	0x80000000,
107	0x20002000,
108	0x80000000,
109	0x20002000,
110	0x80000000,
111	0x20002000,
112	0x80000000,
113	0x20002000,
114	0x80000000,
115	0x20002000,
116	0x80000000,
117	0x20002000,
118	0x80000000,
119	0x20002000,
120	0x80000000,
121	0x20002000,
122	0x00000000, /* PA_SC_VPORT_ZMIN_0 */
123	0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
124
125	0xc0016900,
126	0x000000d4,
127	0x00000000, /* SX_MISC */
128
129	0xc0026900,
130	0x000000d9,
131	0x00000000, /* CP_RINGID */
132	0x00000000, /* CP_VMID */
133
134	0xc0096900,
135	0x00000100,
136	0x00ffffff, /* VGT_MAX_VTX_INDX */
137	0x00000000, /* VGT_MIN_VTX_INDX */
138	0x00000000, /* VGT_INDX_OFFSET */
139	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
140	0x00000000, /* SX_ALPHA_TEST_CONTROL */
141	0x00000000, /* CB_BLEND_RED */
142	0x00000000, /* CB_BLEND_GREEN */
143	0x00000000, /* CB_BLEND_BLUE */
144	0x00000000, /* CB_BLEND_ALPHA */
145
146	0xc0016900,
147	0x00000187,
148	0x00000100, /* SPI_VS_OUT_ID_0 */
149
150	0xc0026900,
151	0x00000191,
152	0x00000100, /* SPI_PS_INPUT_CNTL_0 */
153	0x00000101, /* SPI_PS_INPUT_CNTL_1 */
154
155	0xc0016900,
156	0x000001b1,
157	0x00000000, /* SPI_VS_OUT_CONFIG */
158
159	0xc0106900,
160	0x000001b3,
161	0x20000001, /* SPI_PS_IN_CONTROL_0 */
162	0x00000000, /* SPI_PS_IN_CONTROL_1 */
163	0x00000000, /* SPI_INTERP_CONTROL_0 */
164	0x00000000, /* SPI_INPUT_Z */
165	0x00000000, /* SPI_FOG_CNTL */
166	0x00100000, /* SPI_BARYC_CNTL */
167	0x00000000, /* SPI_PS_IN_CONTROL_2 */
168	0x00000000, /* SPI_COMPUTE_INPUT_CNTL */
169	0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */
170	0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */
171	0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */
172	0x00000000, /* SPI_GPR_MGMT */
173	0x00000000, /* SPI_LDS_MGMT */
174	0x00000000, /* SPI_STACK_MGMT */
175	0x00000000, /* SPI_WAVE_MGMT_1 */
176	0x00000000, /* SPI_WAVE_MGMT_2 */
177
178	0xc0016900,
179	0x000001e0,
180	0x00000000, /* CB_BLEND0_CONTROL */
181
182	0xc00e6900,
183	0x00000200,
184	0x00000000, /* DB_DEPTH_CONTROL */
185	0x00000000, /* DB_EQAA */
186	0x00cc0010, /* CB_COLOR_CONTROL */
187	0x00000210, /* DB_SHADER_CONTROL */
188	0x00010000, /* PA_CL_CLIP_CNTL */
189	0x00000004, /* PA_SU_SC_MODE_CNTL */
190	0x00000100, /* PA_CL_VTE_CNTL */
191	0x00000000, /* PA_CL_VS_OUT_CNTL */
192	0x00000000, /* PA_CL_NANINF_CNTL */
193	0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
194	0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
195	0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
196	0x00000000, /*  */
197	0x00000000, /*  */
198
199	0xc0026900,
200	0x00000229,
201	0x00000000, /* SQ_PGM_START_FS */
202	0x00000000,
203
204	0xc0016900,
205	0x0000023b,
206	0x00000000, /* SQ_LDS_ALLOC_PS */
207
208	0xc0066900,
209	0x00000240,
210	0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
211	0x00000000,
212	0x00000000,
213	0x00000000,
214	0x00000000,
215	0x00000000,
216
217	0xc0046900,
218	0x00000247,
219	0x00000000, /* SQ_GS_VERT_ITEMSIZE */
220	0x00000000,
221	0x00000000,
222	0x00000000,
223
224	0xc0116900,
225	0x00000280,
226	0x00000000, /* PA_SU_POINT_SIZE */
227	0x00000000, /* PA_SU_POINT_MINMAX */
228	0x00000008, /* PA_SU_LINE_CNTL */
229	0x00000000, /* PA_SC_LINE_STIPPLE */
230	0x00000000, /* VGT_OUTPUT_PATH_CNTL */
231	0x00000000, /* VGT_HOS_CNTL */
232	0x00000000,
233	0x00000000,
234	0x00000000,
235	0x00000000,
236	0x00000000,
237	0x00000000,
238	0x00000000,
239	0x00000000,
240	0x00000000,
241	0x00000000,
242	0x00000000, /* VGT_GS_MODE */
243
244	0xc0026900,
245	0x00000292,
246	0x00000000, /* PA_SC_MODE_CNTL_0 */
247	0x00000000, /* PA_SC_MODE_CNTL_1 */
248
249	0xc0016900,
250	0x000002a1,
251	0x00000000, /* VGT_PRIMITIVEID_EN */
252
253	0xc0016900,
254	0x000002a5,
255	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
256
257	0xc0026900,
258	0x000002a8,
259	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
260	0x00000000,
261
262	0xc0026900,
263	0x000002ad,
264	0x00000000, /* VGT_REUSE_OFF */
265	0x00000000,
266
267	0xc0016900,
268	0x000002d5,
269	0x00000000, /* VGT_SHADER_STAGES_EN */
270
271	0xc0016900,
272	0x000002dc,
273	0x0000aa00, /* DB_ALPHA_TO_MASK */
274
275	0xc0066900,
276	0x000002de,
277	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
278	0x00000000,
279	0x00000000,
280	0x00000000,
281	0x00000000,
282	0x00000000,
283
284	0xc0026900,
285	0x000002e5,
286	0x00000000, /* VGT_STRMOUT_CONFIG */
287	0x00000000,
288
289	0xc01b6900,
290	0x000002f5,
291	0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
292	0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
293	0x00000000, /* PA_SC_LINE_CNTL */
294	0x00000000, /* PA_SC_AA_CONFIG */
295	0x00000005, /* PA_SU_VTX_CNTL */
296	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
297	0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
298	0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
299	0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
300	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
301	0x00000000,
302	0x00000000,
303	0x00000000,
304	0x00000000,
305	0x00000000,
306	0x00000000,
307	0x00000000,
308	0x00000000,
309	0x00000000,
310	0x00000000,
311	0x00000000,
312	0x00000000,
313	0x00000000,
314	0x00000000,
315	0x00000000,
316	0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
317	0xffffffff,
318
319	0xc0026900,
320	0x00000316,
321	0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
322	0x00000010, /*  */
323};
324
325const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);
326