1/* $NetBSD: nouveau_nvkm_subdev_fb_ramgk104.c,v 1.4 2021/12/18 23:45:39 riastradh Exp $ */ 2 3/* 4 * Copyright 2013 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs 25 */ 26#include <sys/cdefs.h> 27__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_fb_ramgk104.c,v 1.4 2021/12/18 23:45:39 riastradh Exp $"); 28 29#define gk104_ram(p) container_of((p), struct gk104_ram, base) 30#include "ram.h" 31#include "ramfuc.h" 32 33#include <core/option.h> 34#include <subdev/bios.h> 35#include <subdev/bios/init.h> 36#include <subdev/bios/M0205.h> 37#include <subdev/bios/M0209.h> 38#include <subdev/bios/pll.h> 39#include <subdev/bios/rammap.h> 40#include <subdev/bios/timing.h> 41#include <subdev/clk.h> 42#include <subdev/clk/pll.h> 43#include <subdev/gpio.h> 44 45struct gk104_ramfuc { 46 struct ramfuc base; 47 48 struct nvbios_pll refpll; 49 struct nvbios_pll mempll; 50 51 struct ramfuc_reg r_gpioMV; 52 u32 r_funcMV[2]; 53 struct ramfuc_reg r_gpio2E; 54 u32 r_func2E[2]; 55 struct ramfuc_reg r_gpiotrig; 56 57 struct ramfuc_reg r_0x132020; 58 struct ramfuc_reg r_0x132028; 59 struct ramfuc_reg r_0x132024; 60 struct ramfuc_reg r_0x132030; 61 struct ramfuc_reg r_0x132034; 62 struct ramfuc_reg r_0x132000; 63 struct ramfuc_reg r_0x132004; 64 struct ramfuc_reg r_0x132040; 65 66 struct ramfuc_reg r_0x10f248; 67 struct ramfuc_reg r_0x10f290; 68 struct ramfuc_reg r_0x10f294; 69 struct ramfuc_reg r_0x10f298; 70 struct ramfuc_reg r_0x10f29c; 71 struct ramfuc_reg r_0x10f2a0; 72 struct ramfuc_reg r_0x10f2a4; 73 struct ramfuc_reg r_0x10f2a8; 74 struct ramfuc_reg r_0x10f2ac; 75 struct ramfuc_reg r_0x10f2cc; 76 struct ramfuc_reg r_0x10f2e8; 77 struct ramfuc_reg r_0x10f250; 78 struct ramfuc_reg r_0x10f24c; 79 struct ramfuc_reg r_0x10fec4; 80 struct ramfuc_reg r_0x10fec8; 81 struct ramfuc_reg r_0x10f604; 82 struct ramfuc_reg r_0x10f614; 83 struct ramfuc_reg r_0x10f610; 84 struct ramfuc_reg r_0x100770; 85 struct ramfuc_reg r_0x100778; 86 struct ramfuc_reg r_0x10f224; 87 88 struct ramfuc_reg r_0x10f870; 89 struct ramfuc_reg r_0x10f698; 90 struct ramfuc_reg r_0x10f694; 91 struct ramfuc_reg r_0x10f6b8; 92 struct ramfuc_reg r_0x10f808; 93 struct ramfuc_reg r_0x10f670; 94 struct ramfuc_reg r_0x10f60c; 95 struct ramfuc_reg r_0x10f830; 96 struct ramfuc_reg r_0x1373ec; 97 struct ramfuc_reg r_0x10f800; 98 struct ramfuc_reg r_0x10f82c; 99 100 struct ramfuc_reg r_0x10f978; 101 struct ramfuc_reg r_0x10f910; 102 struct ramfuc_reg r_0x10f914; 103 104 struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */ 105 106 struct ramfuc_reg r_0x62c000; 107 108 struct ramfuc_reg r_0x10f200; 109 110 struct ramfuc_reg r_0x10f210; 111 struct ramfuc_reg r_0x10f310; 112 struct ramfuc_reg r_0x10f314; 113 struct ramfuc_reg r_0x10f318; 114 struct ramfuc_reg r_0x10f090; 115 struct ramfuc_reg r_0x10f69c; 116 struct ramfuc_reg r_0x10f824; 117 struct ramfuc_reg r_0x1373f0; 118 struct ramfuc_reg r_0x1373f4; 119 struct ramfuc_reg r_0x137320; 120 struct ramfuc_reg r_0x10f65c; 121 struct ramfuc_reg r_0x10f6bc; 122 struct ramfuc_reg r_0x100710; 123 struct ramfuc_reg r_0x100750; 124}; 125 126struct gk104_ram { 127 struct nvkm_ram base; 128 struct gk104_ramfuc fuc; 129 130 struct list_head cfg; 131 u32 parts; 132 u32 pmask; 133 u32 pnuts; 134 135 struct nvbios_ramcfg diff; 136 int from; 137 int mode; 138 int N1, fN1, M1, P1; 139 int N2, M2, P2; 140}; 141 142/******************************************************************************* 143 * GDDR5 144 ******************************************************************************/ 145static void 146gk104_ram_train(struct gk104_ramfuc *fuc, u32 mask, u32 data) 147{ 148 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); 149 u32 addr = 0x110974, i; 150 151 ram_mask(fuc, 0x10f910, mask, data); 152 ram_mask(fuc, 0x10f914, mask, data); 153 154 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) { 155 if (ram->pmask & (1 << i)) 156 continue; 157 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000); 158 } 159} 160 161static void 162r1373f4_init(struct gk104_ramfuc *fuc) 163{ 164 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); 165 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); 166 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); 167 const u32 runk0 = ram->fN1 << 16; 168 const u32 runk1 = ram->fN1; 169 170 if (ram->from == 2) { 171 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100); 172 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010); 173 } else { 174 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); 175 } 176 177 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); 178 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); 179 180 /* (re)program refpll, if required */ 181 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef || 182 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) { 183 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); 184 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000); 185 ram_wr32(fuc, 0x137320, 0x00000000); 186 ram_mask(fuc, 0x132030, 0xffff0000, runk0); 187 ram_mask(fuc, 0x132034, 0x0000ffff, runk1); 188 ram_wr32(fuc, 0x132024, rcoef); 189 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000); 190 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001); 191 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); 192 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000); 193 } 194 195 /* (re)program mempll, if required */ 196 if (ram->mode == 2) { 197 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); 198 ram_mask(fuc, 0x132000, 0x80000000, 0x80000000); 199 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); 200 ram_mask(fuc, 0x132004, 0x103fffff, mcoef); 201 ram_mask(fuc, 0x132000, 0x00000001, 0x00000001); 202 ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000); 203 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100); 204 } else { 205 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100); 206 } 207 208 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010); 209} 210 211static void 212r1373f4_fini(struct gk104_ramfuc *fuc) 213{ 214 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); 215 struct nvkm_ram_data *next = ram->base.next; 216 u8 v0 = next->bios.ramcfg_11_03_c0; 217 u8 v1 = next->bios.ramcfg_11_03_30; 218 u32 tmp; 219 220 tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000; 221 ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16)); 222 ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000); 223 if (ram->mode == 2) { 224 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000002); 225 ram_mask(fuc, 0x1373f4, 0x00001100, 0x00000000); 226 } else { 227 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001); 228 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); 229 } 230 ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4); 231} 232 233static void 234gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg, 235 u32 _mask, u32 _data, u32 _copy) 236{ 237 struct nvkm_fb *fb = ram->base.fb; 238 struct ramfuc *fuc = &ram->fuc.base; 239 struct nvkm_device *device = fb->subdev.device; 240 u32 addr = 0x110000 + (reg->addr & 0xfff); 241 u32 mask = _mask | _copy; 242 u32 data = (_data & _mask) | (reg->data & _copy); 243 u32 i; 244 245 for (i = 0; i < 16; i++, addr += 0x1000) { 246 if (ram->pnuts & (1 << i)) { 247 u32 prev = nvkm_rd32(device, addr); 248 u32 next = (prev & ~mask) | data; 249 nvkm_memx_wr32(fuc->memx, addr, next); 250 } 251 } 252} 253#define ram_nuts(s,r,m,d,c) \ 254 gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) 255 256static int 257gk104_ram_calc_gddr5(struct gk104_ram *ram, u32 freq) 258{ 259 struct gk104_ramfuc *fuc = &ram->fuc; 260 struct nvkm_ram_data *next = ram->base.next; 261 int vc = !next->bios.ramcfg_11_02_08; 262 int mv = !next->bios.ramcfg_11_02_04; 263 u32 mask, data; 264 265 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); 266 ram_block(fuc); 267 268 if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) 269 ram_wr32(fuc, 0x62c000, 0x0f0f0000); 270 271 /* MR1: turn termination on early, for some reason.. */ 272 if ((ram->base.mr[1] & 0x03c) != 0x030) { 273 ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c); 274 ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000); 275 } 276 277 if (vc == 1 && ram_have(fuc, gpio2E)) { 278 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); 279 if (temp != ram_rd32(fuc, gpio2E)) { 280 ram_wr32(fuc, gpiotrig, 1); 281 ram_nsec(fuc, 20000); 282 } 283 } 284 285 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); 286 287 gk104_ram_train(fuc, 0x01020000, 0x000c0000); 288 289 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ 290 ram_nsec(fuc, 1000); 291 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 292 ram_nsec(fuc, 1000); 293 294 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); 295 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 296 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 297 ram_wr32(fuc, 0x10f090, 0x00000061); 298 ram_wr32(fuc, 0x10f090, 0xc000007f); 299 ram_nsec(fuc, 1000); 300 301 ram_wr32(fuc, 0x10f698, 0x00000000); 302 ram_wr32(fuc, 0x10f69c, 0x00000000); 303 304 /*XXX: there does appear to be some kind of condition here, simply 305 * modifying these bits in the vbios from the default pl0 306 * entries shows no change. however, the data does appear to 307 * be correct and may be required for the transition back 308 */ 309 mask = 0x800f07e0; 310 data = 0x00030000; 311 if (ram_rd32(fuc, 0x10f978) & 0x00800000) 312 data |= 0x00040000; 313 314 if (1) { 315 data |= 0x800807e0; 316 switch (next->bios.ramcfg_11_03_c0) { 317 case 3: data &= ~0x00000040; break; 318 case 2: data &= ~0x00000100; break; 319 case 1: data &= ~0x80000000; break; 320 case 0: data &= ~0x00000400; break; 321 } 322 323 switch (next->bios.ramcfg_11_03_30) { 324 case 3: data &= ~0x00000020; break; 325 case 2: data &= ~0x00000080; break; 326 case 1: data &= ~0x00080000; break; 327 case 0: data &= ~0x00000200; break; 328 } 329 } 330 331 if (next->bios.ramcfg_11_02_80) 332 mask |= 0x03000000; 333 if (next->bios.ramcfg_11_02_40) 334 mask |= 0x00002000; 335 if (next->bios.ramcfg_11_07_10) 336 mask |= 0x00004000; 337 if (next->bios.ramcfg_11_07_08) 338 mask |= 0x00000003; 339 else { 340 mask |= 0x34000000; 341 if (ram_rd32(fuc, 0x10f978) & 0x00800000) 342 mask |= 0x40000000; 343 } 344 ram_mask(fuc, 0x10f824, mask, data); 345 346 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000); 347 348 if (ram->from == 2 && ram->mode != 2) { 349 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000); 350 ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000); 351 ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004); 352 ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010); 353 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); 354 r1373f4_init(fuc); 355 ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001); 356 r1373f4_fini(fuc); 357 ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001); 358 } else 359 if (ram->from != 2 && ram->mode != 2) { 360 r1373f4_init(fuc); 361 r1373f4_fini(fuc); 362 } 363 364 if (ram_have(fuc, gpioMV)) { 365 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]); 366 if (temp != ram_rd32(fuc, gpioMV)) { 367 ram_wr32(fuc, gpiotrig, 1); 368 ram_nsec(fuc, 64000); 369 } 370 } 371 372 if (next->bios.ramcfg_11_02_40 || 373 next->bios.ramcfg_11_07_10) { 374 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); 375 ram_nsec(fuc, 20000); 376 } 377 378 if (ram->from != 2 && ram->mode == 2) { 379 if (0 /*XXX: Titan */) 380 ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000); 381 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); 382 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002); 383 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010); 384 r1373f4_init(fuc); 385 r1373f4_fini(fuc); 386 ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000); 387 ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000); 388 } else 389 if (ram->from == 2 && ram->mode == 2) { 390 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); 391 r1373f4_init(fuc); 392 r1373f4_fini(fuc); 393 } 394 395 if (ram->mode != 2) /*XXX*/ { 396 if (next->bios.ramcfg_11_07_40) 397 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); 398 } 399 400 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); 401 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); 402 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); 403 404 if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) { 405 ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04); 406 ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04); 407 } else 408 if (!next->bios.ramcfg_11_07_08) { 409 ram_wr32(fuc, 0x10f698, 0x00000000); 410 ram_wr32(fuc, 0x10f69c, 0x00000000); 411 } 412 413 if (ram->mode != 2) { 414 u32 data = 0x01000100 * next->bios.ramcfg_11_04; 415 ram_nuke(fuc, 0x10f694); 416 ram_mask(fuc, 0x10f694, 0xff00ff00, data); 417 } 418 419 if (ram->mode == 2 && next->bios.ramcfg_11_08_10) 420 data = 0x00000080; 421 else 422 data = 0x00000000; 423 ram_mask(fuc, 0x10f60c, 0x00000080, data); 424 425 mask = 0x00070000; 426 data = 0x00000000; 427 if (!next->bios.ramcfg_11_02_80) 428 data |= 0x03000000; 429 if (!next->bios.ramcfg_11_02_40) 430 data |= 0x00002000; 431 if (!next->bios.ramcfg_11_07_10) 432 data |= 0x00004000; 433 if (!next->bios.ramcfg_11_07_08) 434 data |= 0x00000003; 435 else 436 data |= 0x74000000; 437 ram_mask(fuc, 0x10f824, mask, data); 438 439 if (next->bios.ramcfg_11_01_08) 440 data = 0x00000000; 441 else 442 data = 0x00001000; 443 ram_mask(fuc, 0x10f200, 0x00001000, data); 444 445 if (ram_rd32(fuc, 0x10f670) & 0x80000000) { 446 ram_nsec(fuc, 10000); 447 ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000); 448 } 449 450 if (next->bios.ramcfg_11_08_01) 451 data = 0x00100000; 452 else 453 data = 0x00000000; 454 ram_mask(fuc, 0x10f82c, 0x00100000, data); 455 456 data = 0x00000000; 457 if (next->bios.ramcfg_11_08_08) 458 data |= 0x00002000; 459 if (next->bios.ramcfg_11_08_04) 460 data |= 0x00001000; 461 if (next->bios.ramcfg_11_08_02) 462 data |= 0x00004000; 463 ram_mask(fuc, 0x10f830, 0x00007000, data); 464 465 /* PFB timing */ 466 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); 467 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); 468 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); 469 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); 470 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); 471 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); 472 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); 473 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); 474 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); 475 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); 476 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); 477 478 data = mask = 0x00000000; 479 if (ram->diff.ramcfg_11_08_20) { 480 if (next->bios.ramcfg_11_08_20) 481 data |= 0x01000000; 482 mask |= 0x01000000; 483 } 484 ram_mask(fuc, 0x10f200, mask, data); 485 486 data = mask = 0x00000000; 487 if (ram->diff.ramcfg_11_02_03) { 488 data |= next->bios.ramcfg_11_02_03 << 8; 489 mask |= 0x00000300; 490 } 491 if (ram->diff.ramcfg_11_01_10) { 492 if (next->bios.ramcfg_11_01_10) 493 data |= 0x70000000; 494 mask |= 0x70000000; 495 } 496 ram_mask(fuc, 0x10f604, mask, data); 497 498 data = mask = 0x00000000; 499 if (ram->diff.timing_20_30_07) { 500 data |= next->bios.timing_20_30_07 << 28; 501 mask |= 0x70000000; 502 } 503 if (ram->diff.ramcfg_11_01_01) { 504 if (next->bios.ramcfg_11_01_01) 505 data |= 0x00000100; 506 mask |= 0x00000100; 507 } 508 ram_mask(fuc, 0x10f614, mask, data); 509 510 data = mask = 0x00000000; 511 if (ram->diff.timing_20_30_07) { 512 data |= next->bios.timing_20_30_07 << 28; 513 mask |= 0x70000000; 514 } 515 if (ram->diff.ramcfg_11_01_02) { 516 if (next->bios.ramcfg_11_01_02) 517 data |= 0x00000100; 518 mask |= 0x00000100; 519 } 520 ram_mask(fuc, 0x10f610, mask, data); 521 522 mask = 0x33f00000; 523 data = 0x00000000; 524 if (!next->bios.ramcfg_11_01_04) 525 data |= 0x20200000; 526 if (!next->bios.ramcfg_11_07_80) 527 data |= 0x12800000; 528 /*XXX: see note above about there probably being some condition 529 * for the 10f824 stuff that uses ramcfg 3... 530 */ 531 if (next->bios.ramcfg_11_03_f0) { 532 if (next->bios.rammap_11_08_0c) { 533 if (!next->bios.ramcfg_11_07_80) 534 mask |= 0x00000020; 535 else 536 data |= 0x00000020; 537 mask |= 0x00000004; 538 } 539 } else { 540 mask |= 0x40000020; 541 data |= 0x00000004; 542 } 543 544 ram_mask(fuc, 0x10f808, mask, data); 545 546 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); 547 548 data = mask = 0x00000000; 549 if (ram->diff.ramcfg_11_02_03) { 550 data |= next->bios.ramcfg_11_02_03; 551 mask |= 0x00000003; 552 } 553 if (ram->diff.ramcfg_11_01_10) { 554 if (next->bios.ramcfg_11_01_10) 555 data |= 0x00000004; 556 mask |= 0x00000004; 557 } 558 559 if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) { 560 ram_mask(fuc, 0x100750, 0x00000008, 0x00000008); 561 ram_wr32(fuc, 0x100710, 0x00000000); 562 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); 563 } 564 565 data = next->bios.timing_20_30_07 << 8; 566 if (next->bios.ramcfg_11_01_01) 567 data |= 0x80000000; 568 ram_mask(fuc, 0x100778, 0x00000700, data); 569 570 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); 571 data = (next->bios.timing[10] & 0x7f000000) >> 24; 572 if (data < next->bios.timing_20_2c_1fc0) 573 data = next->bios.timing_20_2c_1fc0; 574 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); 575 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); 576 577 ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 | 578 next->bios.timing_20_31_0780 << 17 | 579 next->bios.timing_20_31_0078 << 8 | 580 next->bios.timing_20_31_0007); 581 ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 | 582 next->bios.timing_20_31_7000); 583 584 ram_wr32(fuc, 0x10f090, 0x4000007e); 585 ram_nsec(fuc, 2000); 586 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 587 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 588 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ 589 590 if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) { 591 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); 592 gk104_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ 593 ram_nsec(fuc, 1000); 594 ram_wr32(fuc, 0x10f294, temp); 595 } 596 597 ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]); 598 ram_wr32(fuc, mr[0], ram->base.mr[0]); 599 ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]); 600 ram_nsec(fuc, 1000); 601 ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]); 602 ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */ 603 ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]); 604 ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]); 605 606 if (vc == 0 && ram_have(fuc, gpio2E)) { 607 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]); 608 if (temp != ram_rd32(fuc, gpio2E)) { 609 ram_wr32(fuc, gpiotrig, 1); 610 ram_nsec(fuc, 20000); 611 } 612 } 613 614 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); 615 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ 616 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 617 ram_nsec(fuc, 1000); 618 ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800); 619 620 data = ram_rd32(fuc, 0x10f978); 621 data &= ~0x00046144; 622 data |= 0x0000000b; 623 if (!next->bios.ramcfg_11_07_08) { 624 if (!next->bios.ramcfg_11_07_04) 625 data |= 0x0000200c; 626 else 627 data |= 0x00000000; 628 } else { 629 data |= 0x00040044; 630 } 631 ram_wr32(fuc, 0x10f978, data); 632 633 if (ram->mode == 1) { 634 data = ram_rd32(fuc, 0x10f830) | 0x00000001; 635 ram_wr32(fuc, 0x10f830, data); 636 } 637 638 if (!next->bios.ramcfg_11_07_08) { 639 data = 0x88020000; 640 if ( next->bios.ramcfg_11_07_04) 641 data |= 0x10000000; 642 if (!next->bios.rammap_11_08_10) 643 data |= 0x00080000; 644 } else { 645 data = 0xa40e0000; 646 } 647 gk104_ram_train(fuc, 0xbc0f0000, data); 648 if (1) /* XXX: not always? */ 649 ram_nsec(fuc, 1000); 650 651 if (ram->mode == 2) { /*XXX*/ 652 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004); 653 } 654 655 /* LP3 */ 656 if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5]) 657 ram_nsec(fuc, 1000); 658 659 if (ram->mode != 2) { 660 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); 661 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); 662 } 663 664 if (next->bios.ramcfg_11_07_02) 665 gk104_ram_train(fuc, 0x80020000, 0x01000000); 666 667 ram_unblock(fuc); 668 669 if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) 670 ram_wr32(fuc, 0x62c000, 0x0f0f0f00); 671 672 if (next->bios.rammap_11_08_01) 673 data = 0x00000800; 674 else 675 data = 0x00000000; 676 ram_mask(fuc, 0x10f200, 0x00000800, data); 677 ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800); 678 return 0; 679} 680 681/******************************************************************************* 682 * DDR3 683 ******************************************************************************/ 684 685static void 686nvkm_sddr3_dll_reset(struct gk104_ramfuc *fuc) 687{ 688 ram_nuke(fuc, mr[0]); 689 ram_mask(fuc, mr[0], 0x100, 0x100); 690 ram_mask(fuc, mr[0], 0x100, 0x000); 691} 692 693static void 694nvkm_sddr3_dll_disable(struct gk104_ramfuc *fuc) 695{ 696 u32 mr1_old = ram_rd32(fuc, mr[1]); 697 698 if (!(mr1_old & 0x1)) { 699 ram_mask(fuc, mr[1], 0x1, 0x1); 700 ram_nsec(fuc, 1000); 701 } 702} 703 704static int 705gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq) 706{ 707 struct gk104_ramfuc *fuc = &ram->fuc; 708 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); 709 const u32 runk0 = ram->fN1 << 16; 710 const u32 runk1 = ram->fN1; 711 struct nvkm_ram_data *next = ram->base.next; 712 int vc = !next->bios.ramcfg_11_02_08; 713 int mv = !next->bios.ramcfg_11_02_04; 714 u32 mask, data; 715 716 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); 717 ram_block(fuc); 718 719 if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) 720 ram_wr32(fuc, 0x62c000, 0x0f0f0000); 721 722 if (vc == 1 && ram_have(fuc, gpio2E)) { 723 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); 724 if (temp != ram_rd32(fuc, gpio2E)) { 725 ram_wr32(fuc, gpiotrig, 1); 726 ram_nsec(fuc, 20000); 727 } 728 } 729 730 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); 731 if (next->bios.ramcfg_11_03_f0) 732 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); 733 734 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 735 736 if (next->bios.ramcfg_DLLoff) 737 nvkm_sddr3_dll_disable(fuc); 738 739 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ 740 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 741 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); 742 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 743 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 744 ram_nsec(fuc, 1000); 745 746 ram_wr32(fuc, 0x10f090, 0x00000060); 747 ram_wr32(fuc, 0x10f090, 0xc000007e); 748 749 /*XXX: there does appear to be some kind of condition here, simply 750 * modifying these bits in the vbios from the default pl0 751 * entries shows no change. however, the data does appear to 752 * be correct and may be required for the transition back 753 */ 754 mask = 0x00010000; 755 data = 0x00010000; 756 757 if (1) { 758 mask |= 0x800807e0; 759 data |= 0x800807e0; 760 switch (next->bios.ramcfg_11_03_c0) { 761 case 3: data &= ~0x00000040; break; 762 case 2: data &= ~0x00000100; break; 763 case 1: data &= ~0x80000000; break; 764 case 0: data &= ~0x00000400; break; 765 } 766 767 switch (next->bios.ramcfg_11_03_30) { 768 case 3: data &= ~0x00000020; break; 769 case 2: data &= ~0x00000080; break; 770 case 1: data &= ~0x00080000; break; 771 case 0: data &= ~0x00000200; break; 772 } 773 } 774 775 if (next->bios.ramcfg_11_02_80) 776 mask |= 0x03000000; 777 if (next->bios.ramcfg_11_02_40) 778 mask |= 0x00002000; 779 if (next->bios.ramcfg_11_07_10) 780 mask |= 0x00004000; 781 if (next->bios.ramcfg_11_07_08) 782 mask |= 0x00000003; 783 else 784 mask |= 0x14000000; 785 ram_mask(fuc, 0x10f824, mask, data); 786 787 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000); 788 789 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); 790 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; 791 data |= next->bios.ramcfg_11_03_30 << 16; 792 ram_wr32(fuc, 0x1373ec, data); 793 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); 794 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); 795 796 /* (re)program refpll, if required */ 797 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef || 798 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) { 799 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); 800 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000); 801 ram_wr32(fuc, 0x137320, 0x00000000); 802 ram_mask(fuc, 0x132030, 0xffff0000, runk0); 803 ram_mask(fuc, 0x132034, 0x0000ffff, runk1); 804 ram_wr32(fuc, 0x132024, rcoef); 805 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000); 806 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001); 807 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); 808 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000); 809 } 810 811 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010); 812 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001); 813 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); 814 815 if (ram_have(fuc, gpioMV)) { 816 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]); 817 if (temp != ram_rd32(fuc, gpioMV)) { 818 ram_wr32(fuc, gpiotrig, 1); 819 ram_nsec(fuc, 64000); 820 } 821 } 822 823 if (next->bios.ramcfg_11_02_40 || 824 next->bios.ramcfg_11_07_10) { 825 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); 826 ram_nsec(fuc, 20000); 827 } 828 829 if (ram->mode != 2) /*XXX*/ { 830 if (next->bios.ramcfg_11_07_40) 831 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); 832 } 833 834 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); 835 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); 836 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); 837 838 mask = 0x00010000; 839 data = 0x00000000; 840 if (!next->bios.ramcfg_11_02_80) 841 data |= 0x03000000; 842 if (!next->bios.ramcfg_11_02_40) 843 data |= 0x00002000; 844 if (!next->bios.ramcfg_11_07_10) 845 data |= 0x00004000; 846 if (!next->bios.ramcfg_11_07_08) 847 data |= 0x00000003; 848 else 849 data |= 0x14000000; 850 ram_mask(fuc, 0x10f824, mask, data); 851 ram_nsec(fuc, 1000); 852 853 if (next->bios.ramcfg_11_08_01) 854 data = 0x00100000; 855 else 856 data = 0x00000000; 857 ram_mask(fuc, 0x10f82c, 0x00100000, data); 858 859 /* PFB timing */ 860 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); 861 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); 862 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); 863 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); 864 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); 865 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); 866 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); 867 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); 868 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); 869 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); 870 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); 871 872 mask = 0x33f00000; 873 data = 0x00000000; 874 if (!next->bios.ramcfg_11_01_04) 875 data |= 0x20200000; 876 if (!next->bios.ramcfg_11_07_80) 877 data |= 0x12800000; 878 /*XXX: see note above about there probably being some condition 879 * for the 10f824 stuff that uses ramcfg 3... 880 */ 881 if (next->bios.ramcfg_11_03_f0) { 882 if (next->bios.rammap_11_08_0c) { 883 if (!next->bios.ramcfg_11_07_80) 884 mask |= 0x00000020; 885 else 886 data |= 0x00000020; 887 mask |= 0x08000004; 888 } 889 data |= 0x04000000; 890 } else { 891 mask |= 0x44000020; 892 data |= 0x08000004; 893 } 894 895 ram_mask(fuc, 0x10f808, mask, data); 896 897 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); 898 899 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); 900 901 data = (next->bios.timing[10] & 0x7f000000) >> 24; 902 if (data < next->bios.timing_20_2c_1fc0) 903 data = next->bios.timing_20_2c_1fc0; 904 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); 905 906 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); 907 908 ram_wr32(fuc, 0x10f090, 0x4000007f); 909 ram_nsec(fuc, 1000); 910 911 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 912 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 913 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ 914 ram_nsec(fuc, 1000); 915 916 if (!next->bios.ramcfg_DLLoff) { 917 ram_mask(fuc, mr[1], 0x1, 0x0); 918 nvkm_sddr3_dll_reset(fuc); 919 } 920 921 ram_mask(fuc, mr[2], 0x00000fff, ram->base.mr[2]); 922 ram_mask(fuc, mr[1], 0xffffffff, ram->base.mr[1]); 923 ram_wr32(fuc, mr[0], ram->base.mr[0]); 924 ram_nsec(fuc, 1000); 925 926 if (!next->bios.ramcfg_DLLoff) { 927 nvkm_sddr3_dll_reset(fuc); 928 ram_nsec(fuc, 1000); 929 } 930 931 if (vc == 0 && ram_have(fuc, gpio2E)) { 932 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]); 933 if (temp != ram_rd32(fuc, gpio2E)) { 934 ram_wr32(fuc, gpiotrig, 1); 935 ram_nsec(fuc, 20000); 936 } 937 } 938 939 if (ram->mode != 2) { 940 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); 941 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); 942 } 943 944 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); 945 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ 946 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 947 ram_nsec(fuc, 1000); 948 949 ram_unblock(fuc); 950 951 if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) 952 ram_wr32(fuc, 0x62c000, 0x0f0f0f00); 953 954 if (next->bios.rammap_11_08_01) 955 data = 0x00000800; 956 else 957 data = 0x00000000; 958 ram_mask(fuc, 0x10f200, 0x00000800, data); 959 return 0; 960} 961 962/******************************************************************************* 963 * main hooks 964 ******************************************************************************/ 965 966static int 967gk104_ram_calc_data(struct gk104_ram *ram, u32 khz, struct nvkm_ram_data *data) 968{ 969 struct nvkm_subdev *subdev = &ram->base.fb->subdev; 970 struct nvkm_ram_data *cfg; 971 u32 mhz = khz / 1000; 972 973 list_for_each_entry(cfg, &ram->cfg, head) { 974 if (mhz >= cfg->bios.rammap_min && 975 mhz <= cfg->bios.rammap_max) { 976 *data = *cfg; 977 data->freq = khz; 978 return 0; 979 } 980 } 981 982 nvkm_error(subdev, "ramcfg data for %dMHz not found\n", mhz); 983 return -EINVAL; 984} 985 986static int 987gk104_calc_pll_output(int fN, int M, int N, int P, int clk) 988{ 989 return ((clk * N) + (((u16)(fN + 4096) * clk) >> 13)) / (M * P); 990} 991 992static int 993gk104_pll_calc_hiclk(int target_khz, int crystal, 994 int *N1, int *fN1, int *M1, int *P1, 995 int *N2, int *M2, int *P2) 996{ 997 int best_err = target_khz, p_ref, n_ref; 998 bool upper = false; 999 1000 *M1 = 1; 1001 /* M has to be 1, otherwise it gets unstable */ 1002 *M2 = 1; 1003 /* can be 1 or 2, sticking with 1 for simplicity */ 1004 *P2 = 1; 1005 1006 for (p_ref = 0x7; p_ref >= 0x5; --p_ref) { 1007 for (n_ref = 0x25; n_ref <= 0x2b; ++n_ref) { 1008 int cur_N, cur_clk, cur_err; 1009 1010 cur_clk = gk104_calc_pll_output(0, 1, n_ref, p_ref, crystal); 1011 cur_N = target_khz / cur_clk; 1012 cur_err = target_khz 1013 - gk104_calc_pll_output(0xf000, 1, cur_N, 1, cur_clk); 1014 1015 /* we found a better combination */ 1016 if (cur_err < best_err) { 1017 best_err = cur_err; 1018 *N2 = cur_N; 1019 *N1 = n_ref; 1020 *P1 = p_ref; 1021 upper = false; 1022 } 1023 1024 cur_N += 1; 1025 cur_err = gk104_calc_pll_output(0xf000, 1, cur_N, 1, cur_clk) 1026 - target_khz; 1027 if (cur_err < best_err) { 1028 best_err = cur_err; 1029 *N2 = cur_N; 1030 *N1 = n_ref; 1031 *P1 = p_ref; 1032 upper = true; 1033 } 1034 } 1035 } 1036 1037 /* adjust fN to get closer to the target clock */ 1038 *fN1 = (u16)((((best_err / *N2 * *P2) * (*P1 * *M1)) << 13) / crystal); 1039 if (upper) 1040 *fN1 = (u16)(1 - *fN1); 1041 1042 return gk104_calc_pll_output(*fN1, 1, *N1, *P1, crystal); 1043} 1044 1045static int 1046gk104_ram_calc_xits(struct gk104_ram *ram, struct nvkm_ram_data *next) 1047{ 1048 struct gk104_ramfuc *fuc = &ram->fuc; 1049 struct nvkm_subdev *subdev = &ram->base.fb->subdev; 1050 int refclk, i; 1051 int ret; 1052 1053 ret = ram_init(fuc, ram->base.fb); 1054 if (ret) 1055 return ret; 1056 1057 ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1; 1058 ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f; 1059 1060 /* XXX: this is *not* what nvidia do. on fermi nvidia generally 1061 * select, based on some unknown condition, one of the two possible 1062 * reference frequencies listed in the vbios table for mempll and 1063 * program refpll to that frequency. 1064 * 1065 * so far, i've seen very weird values being chosen by nvidia on 1066 * kepler boards, no idea how/why they're chosen. 1067 */ 1068 refclk = next->freq; 1069 if (ram->mode == 2) { 1070 ret = gk104_pll_calc_hiclk(next->freq, subdev->device->crystal, 1071 &ram->N1, &ram->fN1, &ram->M1, &ram->P1, 1072 &ram->N2, &ram->M2, &ram->P2); 1073 fuc->mempll.refclk = ret; 1074 if (ret <= 0) { 1075 nvkm_error(subdev, "unable to calc plls\n"); 1076 return -EINVAL; 1077 } 1078 nvkm_debug(subdev, "successfully calced PLLs for clock %i kHz" 1079 " (refclock: %i kHz)\n", next->freq, ret); 1080 } else { 1081 /* calculate refpll coefficients */ 1082 ret = gt215_pll_calc(subdev, &fuc->refpll, refclk, &ram->N1, 1083 &ram->fN1, &ram->M1, &ram->P1); 1084 fuc->mempll.refclk = ret; 1085 if (ret <= 0) { 1086 nvkm_error(subdev, "unable to calc refpll\n"); 1087 return -EINVAL; 1088 } 1089 } 1090 1091 for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) { 1092 if (ram_have(fuc, mr[i])) 1093 ram->base.mr[i] = ram_rd32(fuc, mr[i]); 1094 } 1095 ram->base.freq = next->freq; 1096 1097 switch (ram->base.type) { 1098 case NVKM_RAM_TYPE_DDR3: 1099 ret = nvkm_sddr3_calc(&ram->base); 1100 if (ret == 0) 1101 ret = gk104_ram_calc_sddr3(ram, next->freq); 1102 break; 1103 case NVKM_RAM_TYPE_GDDR5: 1104 ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0); 1105 if (ret == 0) 1106 ret = gk104_ram_calc_gddr5(ram, next->freq); 1107 break; 1108 default: 1109 ret = -ENOSYS; 1110 break; 1111 } 1112 1113 return ret; 1114} 1115 1116int 1117gk104_ram_calc(struct nvkm_ram *base, u32 freq) 1118{ 1119 struct gk104_ram *ram = gk104_ram(base); 1120 struct nvkm_clk *clk = ram->base.fb->subdev.device->clk; 1121 struct nvkm_ram_data *xits = &ram->base.xition; 1122 struct nvkm_ram_data *copy; 1123 int ret; 1124 1125 if (ram->base.next == NULL) { 1126 ret = gk104_ram_calc_data(ram, 1127 nvkm_clk_read(clk, nv_clk_src_mem), 1128 &ram->base.former); 1129 if (ret) 1130 return ret; 1131 1132 ret = gk104_ram_calc_data(ram, freq, &ram->base.target); 1133 if (ret) 1134 return ret; 1135 1136 if (ram->base.target.freq < ram->base.former.freq) { 1137 *xits = ram->base.target; 1138 copy = &ram->base.former; 1139 } else { 1140 *xits = ram->base.former; 1141 copy = &ram->base.target; 1142 } 1143 1144 xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04; 1145 xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03; 1146 xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07; 1147 1148 ram->base.next = &ram->base.target; 1149 if (memcmp(xits, &ram->base.former, sizeof(xits->bios))) 1150 ram->base.next = &ram->base.xition; 1151 } else { 1152 BUG_ON(ram->base.next != &ram->base.xition); 1153 ram->base.next = &ram->base.target; 1154 } 1155 1156 return gk104_ram_calc_xits(ram, ram->base.next); 1157} 1158 1159static void 1160gk104_ram_prog_0(struct gk104_ram *ram, u32 freq) 1161{ 1162 struct nvkm_device *device = ram->base.fb->subdev.device; 1163 struct nvkm_ram_data *cfg; 1164 u32 mhz = freq / 1000; 1165 u32 mask, data; 1166 1167 list_for_each_entry(cfg, &ram->cfg, head) { 1168 if (mhz >= cfg->bios.rammap_min && 1169 mhz <= cfg->bios.rammap_max) 1170 break; 1171 } 1172 1173 if (&cfg->head == &ram->cfg) 1174 return; 1175 1176 if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) { 1177 data |= cfg->bios.rammap_11_0a_03fe << 12; 1178 mask |= 0x001ff000; 1179 } 1180 if (ram->diff.rammap_11_09_01ff) { 1181 data |= cfg->bios.rammap_11_09_01ff; 1182 mask |= 0x000001ff; 1183 } 1184 nvkm_mask(device, 0x10f468, mask, data); 1185 1186 if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) { 1187 data |= cfg->bios.rammap_11_0a_0400; 1188 mask |= 0x00000001; 1189 } 1190 nvkm_mask(device, 0x10f420, mask, data); 1191 1192 if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) { 1193 data |= cfg->bios.rammap_11_0a_0800; 1194 mask |= 0x00000001; 1195 } 1196 nvkm_mask(device, 0x10f430, mask, data); 1197 1198 if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) { 1199 data |= cfg->bios.rammap_11_0b_01f0; 1200 mask |= 0x0000001f; 1201 } 1202 nvkm_mask(device, 0x10f400, mask, data); 1203 1204 if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) { 1205 data |= cfg->bios.rammap_11_0b_0200 << 9; 1206 mask |= 0x00000200; 1207 } 1208 nvkm_mask(device, 0x10f410, mask, data); 1209 1210 if (mask = 0, data = 0, ram->diff.rammap_11_0d) { 1211 data |= cfg->bios.rammap_11_0d << 16; 1212 mask |= 0x00ff0000; 1213 } 1214 if (ram->diff.rammap_11_0f) { 1215 data |= cfg->bios.rammap_11_0f << 8; 1216 mask |= 0x0000ff00; 1217 } 1218 nvkm_mask(device, 0x10f440, mask, data); 1219 1220 if (mask = 0, data = 0, ram->diff.rammap_11_0e) { 1221 data |= cfg->bios.rammap_11_0e << 8; 1222 mask |= 0x0000ff00; 1223 } 1224 if (ram->diff.rammap_11_0b_0800) { 1225 data |= cfg->bios.rammap_11_0b_0800 << 7; 1226 mask |= 0x00000080; 1227 } 1228 if (ram->diff.rammap_11_0b_0400) { 1229 data |= cfg->bios.rammap_11_0b_0400 << 5; 1230 mask |= 0x00000020; 1231 } 1232 nvkm_mask(device, 0x10f444, mask, data); 1233} 1234 1235int 1236gk104_ram_prog(struct nvkm_ram *base) 1237{ 1238 struct gk104_ram *ram = gk104_ram(base); 1239 struct gk104_ramfuc *fuc = &ram->fuc; 1240 struct nvkm_device *device = ram->base.fb->subdev.device; 1241 struct nvkm_ram_data *next = ram->base.next; 1242 1243 if (!nvkm_boolopt(device->cfgopt, "NvMemExec", true)) { 1244 ram_exec(fuc, false); 1245 return (ram->base.next == &ram->base.xition); 1246 } 1247 1248 gk104_ram_prog_0(ram, 1000); 1249 ram_exec(fuc, true); 1250 gk104_ram_prog_0(ram, next->freq); 1251 1252 return (ram->base.next == &ram->base.xition); 1253} 1254 1255void 1256gk104_ram_tidy(struct nvkm_ram *base) 1257{ 1258 struct gk104_ram *ram = gk104_ram(base); 1259 ram->base.next = NULL; 1260 ram_exec(&ram->fuc, false); 1261} 1262 1263struct gk104_ram_train { 1264 u16 mask; 1265 struct nvbios_M0209S remap; 1266 struct nvbios_M0209S type00; 1267 struct nvbios_M0209S type01; 1268 struct nvbios_M0209S type04; 1269 struct nvbios_M0209S type06; 1270 struct nvbios_M0209S type07; 1271 struct nvbios_M0209S type08; 1272 struct nvbios_M0209S type09; 1273}; 1274 1275static int 1276gk104_ram_train_type(struct nvkm_ram *ram, int i, u8 ramcfg, 1277 struct gk104_ram_train *train) 1278{ 1279 struct nvkm_bios *bios = ram->fb->subdev.device->bios; 1280 struct nvbios_M0205E M0205E; 1281 struct nvbios_M0205S M0205S; 1282 struct nvbios_M0209E M0209E; 1283 struct nvbios_M0209S *remap = &train->remap; 1284 struct nvbios_M0209S *value; 1285 u8 ver, hdr, cnt, len; 1286 u32 data; 1287 1288 /* determine type of data for this index */ 1289 if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E))) 1290 return -ENOENT; 1291 1292 switch (M0205E.type) { 1293 case 0x00: value = &train->type00; break; 1294 case 0x01: value = &train->type01; break; 1295 case 0x04: value = &train->type04; break; 1296 case 0x06: value = &train->type06; break; 1297 case 0x07: value = &train->type07; break; 1298 case 0x08: value = &train->type08; break; 1299 case 0x09: value = &train->type09; break; 1300 default: 1301 return 0; 1302 } 1303 1304 /* training data index determined by ramcfg strap */ 1305 if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S))) 1306 return -EINVAL; 1307 i = M0205S.data; 1308 1309 /* training data format information */ 1310 if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E))) 1311 return -EINVAL; 1312 1313 /* ... and the raw data */ 1314 if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value))) 1315 return -EINVAL; 1316 1317 if (M0209E.v02_07 == 2) { 1318 /* of course! why wouldn't we have a pointer to another entry 1319 * in the same table, and use the first one as an array of 1320 * remap indices... 1321 */ 1322 if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr, 1323 remap))) 1324 return -EINVAL; 1325 1326 for (i = 0; i < ARRAY_SIZE(value->data); i++) 1327 value->data[i] = remap->data[value->data[i]]; 1328 } else 1329 if (M0209E.v02_07 != 1) 1330 return -EINVAL; 1331 1332 train->mask |= 1 << M0205E.type; 1333 return 0; 1334} 1335 1336static int 1337gk104_ram_train_init_0(struct nvkm_ram *ram, struct gk104_ram_train *train) 1338{ 1339 struct nvkm_subdev *subdev = &ram->fb->subdev; 1340 struct nvkm_device *device = subdev->device; 1341 int i, j; 1342 1343 if ((train->mask & 0x03d3) != 0x03d3) { 1344 nvkm_warn(subdev, "missing link training data\n"); 1345 return -EINVAL; 1346 } 1347 1348 for (i = 0; i < 0x30; i++) { 1349 for (j = 0; j < 8; j += 4) { 1350 nvkm_wr32(device, 0x10f968 + j, 0x00000000 | (i << 8)); 1351 nvkm_wr32(device, 0x10f920 + j, 0x00000000 | 1352 train->type08.data[i] << 4 | 1353 train->type06.data[i]); 1354 nvkm_wr32(device, 0x10f918 + j, train->type00.data[i]); 1355 nvkm_wr32(device, 0x10f920 + j, 0x00000100 | 1356 train->type09.data[i] << 4 | 1357 train->type07.data[i]); 1358 nvkm_wr32(device, 0x10f918 + j, train->type01.data[i]); 1359 } 1360 } 1361 1362 for (j = 0; j < 8; j += 4) { 1363 for (i = 0; i < 0x100; i++) { 1364 nvkm_wr32(device, 0x10f968 + j, i); 1365 nvkm_wr32(device, 0x10f900 + j, train->type04.data[i]); 1366 } 1367 } 1368 1369 return 0; 1370} 1371 1372static int 1373gk104_ram_train_init(struct nvkm_ram *ram) 1374{ 1375 u8 ramcfg = nvbios_ramcfg_index(&ram->fb->subdev); 1376 struct gk104_ram_train *train; 1377 int ret, i; 1378 1379 if (!(train = kzalloc(sizeof(*train), GFP_KERNEL))) 1380 return -ENOMEM; 1381 1382 for (i = 0; i < 0x100; i++) { 1383 ret = gk104_ram_train_type(ram, i, ramcfg, train); 1384 if (ret && ret != -ENOENT) 1385 break; 1386 } 1387 1388 switch (ram->type) { 1389 case NVKM_RAM_TYPE_GDDR5: 1390 ret = gk104_ram_train_init_0(ram, train); 1391 break; 1392 default: 1393 ret = 0; 1394 break; 1395 } 1396 1397 kfree(train); 1398 return ret; 1399} 1400 1401int 1402gk104_ram_init(struct nvkm_ram *ram) 1403{ 1404 struct nvkm_subdev *subdev = &ram->fb->subdev; 1405 struct nvkm_device *device = subdev->device; 1406 struct nvkm_bios *bios = device->bios; 1407 u8 ver, hdr, cnt, len, snr, ssz; 1408 u32 data, save; 1409 int i; 1410 1411 /* run a bunch of tables from rammap table. there's actually 1412 * individual pointers for each rammap entry too, but, nvidia 1413 * seem to just run the last two entries' scripts early on in 1414 * their init, and never again.. we'll just run 'em all once 1415 * for now. 1416 * 1417 * i strongly suspect that each script is for a separate mode 1418 * (likely selected by 0x10f65c's lower bits?), and the 1419 * binary driver skips the one that's already been setup by 1420 * the init tables. 1421 */ 1422 data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); 1423 if (!data || hdr < 0x15) 1424 return -EINVAL; 1425 1426 cnt = nvbios_rd08(bios, data + 0x14); /* guess at count */ 1427 data = nvbios_rd32(bios, data + 0x10); /* guess u32... */ 1428 save = nvkm_rd32(device, 0x10f65c) & 0x000000f0; 1429 for (i = 0; i < cnt; i++, data += 4) { 1430 if (i != save >> 4) { 1431 nvkm_mask(device, 0x10f65c, 0x000000f0, i << 4); 1432 nvbios_init(subdev, nvbios_rd32(bios, data)); 1433 } 1434 } 1435 nvkm_mask(device, 0x10f65c, 0x000000f0, save); 1436 nvkm_mask(device, 0x10f584, 0x11000000, 0x00000000); 1437 nvkm_wr32(device, 0x10ecc0, 0xffffffff); 1438 nvkm_mask(device, 0x10f160, 0x00000010, 0x00000010); 1439 1440 return gk104_ram_train_init(ram); 1441} 1442 1443static int 1444gk104_ram_ctor_data(struct gk104_ram *ram, u8 ramcfg, int i) 1445{ 1446 struct nvkm_bios *bios = ram->base.fb->subdev.device->bios; 1447 struct nvkm_ram_data *cfg; 1448 struct nvbios_ramcfg *d = &ram->diff; 1449 struct nvbios_ramcfg *p, *n; 1450 u8 ver, hdr, cnt, len; 1451 u32 data; 1452 int ret; 1453 1454 if (!(cfg = kmalloc(sizeof(*cfg), GFP_KERNEL))) 1455 return -ENOMEM; 1456 p = &list_last_entry(&ram->cfg, typeof(*cfg), head)->bios; 1457 n = &cfg->bios; 1458 1459 /* memory config data for a range of target frequencies */ 1460 data = nvbios_rammapEp(bios, i, &ver, &hdr, &cnt, &len, &cfg->bios); 1461 if (ret = -ENOENT, !data) 1462 goto done; 1463 if (ret = -ENOSYS, ver != 0x11 || hdr < 0x12) 1464 goto done; 1465 1466 /* ... and a portion specific to the attached memory */ 1467 data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, ramcfg, 1468 &ver, &hdr, &cfg->bios); 1469 if (ret = -EINVAL, !data) 1470 goto done; 1471 if (ret = -ENOSYS, ver != 0x11 || hdr < 0x0a) 1472 goto done; 1473 1474 /* lookup memory timings, if bios says they're present */ 1475 if (cfg->bios.ramcfg_timing != 0xff) { 1476 data = nvbios_timingEp(bios, cfg->bios.ramcfg_timing, 1477 &ver, &hdr, &cnt, &len, 1478 &cfg->bios); 1479 if (ret = -EINVAL, !data) 1480 goto done; 1481 if (ret = -ENOSYS, ver != 0x20 || hdr < 0x33) 1482 goto done; 1483 } 1484 1485 list_add_tail(&cfg->head, &ram->cfg); 1486 if (ret = 0, i == 0) 1487 goto done; 1488 1489 d->rammap_11_0a_03fe |= p->rammap_11_0a_03fe != n->rammap_11_0a_03fe; 1490 d->rammap_11_09_01ff |= p->rammap_11_09_01ff != n->rammap_11_09_01ff; 1491 d->rammap_11_0a_0400 |= p->rammap_11_0a_0400 != n->rammap_11_0a_0400; 1492 d->rammap_11_0a_0800 |= p->rammap_11_0a_0800 != n->rammap_11_0a_0800; 1493 d->rammap_11_0b_01f0 |= p->rammap_11_0b_01f0 != n->rammap_11_0b_01f0; 1494 d->rammap_11_0b_0200 |= p->rammap_11_0b_0200 != n->rammap_11_0b_0200; 1495 d->rammap_11_0d |= p->rammap_11_0d != n->rammap_11_0d; 1496 d->rammap_11_0f |= p->rammap_11_0f != n->rammap_11_0f; 1497 d->rammap_11_0e |= p->rammap_11_0e != n->rammap_11_0e; 1498 d->rammap_11_0b_0800 |= p->rammap_11_0b_0800 != n->rammap_11_0b_0800; 1499 d->rammap_11_0b_0400 |= p->rammap_11_0b_0400 != n->rammap_11_0b_0400; 1500 d->ramcfg_11_01_01 |= p->ramcfg_11_01_01 != n->ramcfg_11_01_01; 1501 d->ramcfg_11_01_02 |= p->ramcfg_11_01_02 != n->ramcfg_11_01_02; 1502 d->ramcfg_11_01_10 |= p->ramcfg_11_01_10 != n->ramcfg_11_01_10; 1503 d->ramcfg_11_02_03 |= p->ramcfg_11_02_03 != n->ramcfg_11_02_03; 1504 d->ramcfg_11_08_20 |= p->ramcfg_11_08_20 != n->ramcfg_11_08_20; 1505 d->timing_20_30_07 |= p->timing_20_30_07 != n->timing_20_30_07; 1506done: 1507 if (ret) 1508 kfree(cfg); 1509 return ret; 1510} 1511 1512void * 1513gk104_ram_dtor(struct nvkm_ram *base) 1514{ 1515 struct gk104_ram *ram = gk104_ram(base); 1516 struct nvkm_ram_data *cfg, *tmp; 1517 1518 list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) { 1519 kfree(cfg); 1520 } 1521 1522 return ram; 1523} 1524 1525int 1526gk104_ram_new_(const struct nvkm_ram_func *func, struct nvkm_fb *fb, 1527 struct nvkm_ram **pram) 1528{ 1529 struct nvkm_subdev *subdev = &fb->subdev; 1530 struct nvkm_device *device = subdev->device; 1531 struct nvkm_bios *bios = device->bios; 1532 struct dcb_gpio_func gpio; 1533 struct gk104_ram *ram; 1534 int ret, i; 1535 u8 ramcfg = nvbios_ramcfg_index(subdev); 1536 u32 tmp; 1537 1538 if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL))) 1539 return -ENOMEM; 1540 *pram = &ram->base; 1541 1542 ret = gf100_ram_ctor(func, fb, &ram->base); 1543 if (ret) 1544 return ret; 1545 1546 INIT_LIST_HEAD(&ram->cfg); 1547 1548 /* calculate a mask of differently configured memory partitions, 1549 * because, of course reclocking wasn't complicated enough 1550 * already without having to treat some of them differently to 1551 * the others.... 1552 */ 1553 ram->parts = nvkm_rd32(device, 0x022438); 1554 ram->pmask = nvkm_rd32(device, 0x022554); 1555 ram->pnuts = 0; 1556 for (i = 0, tmp = 0; i < ram->parts; i++) { 1557 if (!(ram->pmask & (1 << i))) { 1558 u32 cfg1 = nvkm_rd32(device, 0x110204 + (i * 0x1000)); 1559 if (tmp && tmp != cfg1) { 1560 ram->pnuts |= (1 << i); 1561 continue; 1562 } 1563 tmp = cfg1; 1564 } 1565 } 1566 1567 /* parse bios data for all rammap table entries up-front, and 1568 * build information on whether certain fields differ between 1569 * any of the entries. 1570 * 1571 * the binary driver appears to completely ignore some fields 1572 * when all entries contain the same value. at first, it was 1573 * hoped that these were mere optimisations and the bios init 1574 * tables had configured as per the values here, but there is 1575 * evidence now to suggest that this isn't the case and we do 1576 * need to treat this condition as a "don't touch" indicator. 1577 */ 1578 for (i = 0; !ret; i++) { 1579 ret = gk104_ram_ctor_data(ram, ramcfg, i); 1580 if (ret && ret != -ENOENT) { 1581 nvkm_error(subdev, "failed to parse ramcfg data\n"); 1582 return ret; 1583 } 1584 } 1585 1586 /* parse bios data for both pll's */ 1587 ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll); 1588 if (ret) { 1589 nvkm_error(subdev, "mclk refpll data not found\n"); 1590 return ret; 1591 } 1592 1593 ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll); 1594 if (ret) { 1595 nvkm_error(subdev, "mclk pll data not found\n"); 1596 return ret; 1597 } 1598 1599 /* lookup memory voltage gpios */ 1600 ret = nvkm_gpio_find(device->gpio, 0, 0x18, DCB_GPIO_UNUSED, &gpio); 1601 if (ret == 0) { 1602 ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (gpio.line * 0x04)); 1603 ram->fuc.r_funcMV[0] = (gpio.log[0] ^ 2) << 12; 1604 ram->fuc.r_funcMV[1] = (gpio.log[1] ^ 2) << 12; 1605 } 1606 1607 ret = nvkm_gpio_find(device->gpio, 0, 0x2e, DCB_GPIO_UNUSED, &gpio); 1608 if (ret == 0) { 1609 ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (gpio.line * 0x04)); 1610 ram->fuc.r_func2E[0] = (gpio.log[0] ^ 2) << 12; 1611 ram->fuc.r_func2E[1] = (gpio.log[1] ^ 2) << 12; 1612 } 1613 1614 ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604); 1615 1616 ram->fuc.r_0x132020 = ramfuc_reg(0x132020); 1617 ram->fuc.r_0x132028 = ramfuc_reg(0x132028); 1618 ram->fuc.r_0x132024 = ramfuc_reg(0x132024); 1619 ram->fuc.r_0x132030 = ramfuc_reg(0x132030); 1620 ram->fuc.r_0x132034 = ramfuc_reg(0x132034); 1621 ram->fuc.r_0x132000 = ramfuc_reg(0x132000); 1622 ram->fuc.r_0x132004 = ramfuc_reg(0x132004); 1623 ram->fuc.r_0x132040 = ramfuc_reg(0x132040); 1624 1625 ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248); 1626 ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290); 1627 ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294); 1628 ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298); 1629 ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c); 1630 ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0); 1631 ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4); 1632 ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8); 1633 ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac); 1634 ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc); 1635 ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8); 1636 ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250); 1637 ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c); 1638 ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4); 1639 ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8); 1640 ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604); 1641 ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614); 1642 ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610); 1643 ram->fuc.r_0x100770 = ramfuc_reg(0x100770); 1644 ram->fuc.r_0x100778 = ramfuc_reg(0x100778); 1645 ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224); 1646 1647 ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870); 1648 ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698); 1649 ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694); 1650 ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8); 1651 ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808); 1652 ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670); 1653 ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c); 1654 ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830); 1655 ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec); 1656 ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800); 1657 ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c); 1658 1659 ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978); 1660 ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910); 1661 ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914); 1662 1663 switch (ram->base.type) { 1664 case NVKM_RAM_TYPE_GDDR5: 1665 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); 1666 ram->fuc.r_mr[1] = ramfuc_reg(0x10f330); 1667 ram->fuc.r_mr[2] = ramfuc_reg(0x10f334); 1668 ram->fuc.r_mr[3] = ramfuc_reg(0x10f338); 1669 ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c); 1670 ram->fuc.r_mr[5] = ramfuc_reg(0x10f340); 1671 ram->fuc.r_mr[6] = ramfuc_reg(0x10f344); 1672 ram->fuc.r_mr[7] = ramfuc_reg(0x10f348); 1673 ram->fuc.r_mr[8] = ramfuc_reg(0x10f354); 1674 ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c); 1675 break; 1676 case NVKM_RAM_TYPE_DDR3: 1677 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); 1678 ram->fuc.r_mr[1] = ramfuc_reg(0x10f304); 1679 ram->fuc.r_mr[2] = ramfuc_reg(0x10f320); 1680 break; 1681 default: 1682 break; 1683 } 1684 1685 ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000); 1686 ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200); 1687 ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210); 1688 ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310); 1689 ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314); 1690 ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318); 1691 ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090); 1692 ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c); 1693 ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824); 1694 ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0); 1695 ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4); 1696 ram->fuc.r_0x137320 = ramfuc_reg(0x137320); 1697 ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c); 1698 ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc); 1699 ram->fuc.r_0x100710 = ramfuc_reg(0x100710); 1700 ram->fuc.r_0x100750 = ramfuc_reg(0x100750); 1701 return 0; 1702} 1703 1704static const struct nvkm_ram_func 1705gk104_ram = { 1706 .upper = 0x0200000000ULL, 1707 .probe_fbp = gf100_ram_probe_fbp, 1708 .probe_fbp_amount = gf108_ram_probe_fbp_amount, 1709 .probe_fbpa_amount = gf100_ram_probe_fbpa_amount, 1710 .dtor = gk104_ram_dtor, 1711 .init = gk104_ram_init, 1712 .calc = gk104_ram_calc, 1713 .prog = gk104_ram_prog, 1714 .tidy = gk104_ram_tidy, 1715}; 1716 1717int 1718gk104_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) 1719{ 1720 return gk104_ram_new_(&gk104_ram, fb, pram); 1721} 1722