1/* $NetBSD: nouveau_nvkm_subdev_devinit_nv04.c,v 1.4 2021/12/18 23:45:39 riastradh Exp $ */ 2 3/* 4 * Copyright (C) 2010 Francisco Jerez. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sublicense, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 22 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 23 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 24 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28#include <sys/cdefs.h> 29__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_devinit_nv04.c,v 1.4 2021/12/18 23:45:39 riastradh Exp $"); 30 31#include "nv04.h" 32#include "fbmem.h" 33 34#include <subdev/bios.h> 35#include <subdev/bios/init.h> 36#include <subdev/bios/pll.h> 37#include <subdev/clk/pll.h> 38#include <subdev/vga.h> 39 40static void 41nv04_devinit_meminit(struct nvkm_devinit *init) 42{ 43 struct nvkm_subdev *subdev = &init->subdev; 44 struct nvkm_device *device = subdev->device; 45 u32 patt = 0xdeadbeef; 46 struct io_mapping *fb; 47 int i; 48 49 /* Map the framebuffer aperture */ 50 fb = fbmem_init(device); 51 if (!fb) { 52 nvkm_error(subdev, "failed to map fb\n"); 53 return; 54 } 55 56 /* Sequencer and refresh off */ 57 nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) | 0x20); 58 nvkm_mask(device, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); 59 60 nvkm_mask(device, NV04_PFB_BOOT_0, ~0, 61 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB | 62 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 63 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT); 64 65 for (i = 0; i < 4; i++) 66 fbmem_poke(fb, 4 * i, patt); 67 68 fbmem_poke(fb, 0x400000, patt + 1); 69 70 if (fbmem_peek(fb, 0) == patt + 1) { 71 nvkm_mask(device, NV04_PFB_BOOT_0, 72 NV04_PFB_BOOT_0_RAM_TYPE, 73 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT); 74 nvkm_mask(device, NV04_PFB_DEBUG_0, 75 NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 76 77 for (i = 0; i < 4; i++) 78 fbmem_poke(fb, 4 * i, patt); 79 80 if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff)) 81 nvkm_mask(device, NV04_PFB_BOOT_0, 82 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 83 NV04_PFB_BOOT_0_RAM_AMOUNT, 84 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 85 } else 86 if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) { 87 nvkm_mask(device, NV04_PFB_BOOT_0, 88 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 89 NV04_PFB_BOOT_0_RAM_AMOUNT, 90 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 91 } else 92 if (fbmem_peek(fb, 0) != patt) { 93 if (fbmem_readback(fb, 0x800000, patt)) 94 nvkm_mask(device, NV04_PFB_BOOT_0, 95 NV04_PFB_BOOT_0_RAM_AMOUNT, 96 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 97 else 98 nvkm_mask(device, NV04_PFB_BOOT_0, 99 NV04_PFB_BOOT_0_RAM_AMOUNT, 100 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 101 102 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 103 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT); 104 } else 105 if (!fbmem_readback(fb, 0x800000, patt)) { 106 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 107 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 108 109 } 110 111 /* Refresh on, sequencer on */ 112 nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 113 nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) & ~0x20); 114 fbmem_fini(fb); 115} 116 117static int 118powerctrl_1_shift(int chip_version, int reg) 119{ 120 int shift = -4; 121 122 if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20) 123 return shift; 124 125 switch (reg) { 126 case 0x680520: 127 shift += 4; /* fall through */ 128 case 0x680508: 129 shift += 4; /* fall through */ 130 case 0x680504: 131 shift += 4; /* fall through */ 132 case 0x680500: 133 shift += 4; 134 } 135 136 /* 137 * the shift for vpll regs is only used for nv3x chips with a single 138 * stage pll 139 */ 140 if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 || 141 chip_version == 0x36 || chip_version >= 0x40)) 142 shift = -4; 143 144 return shift; 145} 146 147void 148setPLL_single(struct nvkm_devinit *init, u32 reg, 149 struct nvkm_pll_vals *pv) 150{ 151 struct nvkm_device *device = init->subdev.device; 152 int chip_version = device->bios->version.chip; 153 uint32_t oldpll = nvkm_rd32(device, reg); 154 int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff; 155 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; 156 uint32_t saved_powerctrl_1 = 0; 157 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg); 158 159 if (oldpll == pll) 160 return; /* already set */ 161 162 if (shift_powerctrl_1 >= 0) { 163 saved_powerctrl_1 = nvkm_rd32(device, 0x001584); 164 nvkm_wr32(device, 0x001584, 165 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 166 1 << shift_powerctrl_1); 167 } 168 169 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) 170 /* upclock -- write new post divider first */ 171 nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff)); 172 else 173 /* downclock -- write new NM first */ 174 nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1); 175 176 if ((chip_version < 0x17 || chip_version == 0x1a) && 177 chip_version != 0x11) 178 /* wait a bit on older chips */ 179 msleep(64); 180 nvkm_rd32(device, reg); 181 182 /* then write the other half as well */ 183 nvkm_wr32(device, reg, pll); 184 185 if (shift_powerctrl_1 >= 0) 186 nvkm_wr32(device, 0x001584, saved_powerctrl_1); 187} 188 189static uint32_t 190new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) 191{ 192 bool head_a = (reg1 == 0x680508); 193 194 if (ss) /* single stage pll mode */ 195 ramdac580 |= head_a ? 0x00000100 : 0x10000000; 196 else 197 ramdac580 &= head_a ? 0xfffffeff : 0xefffffff; 198 199 return ramdac580; 200} 201 202void 203setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1, 204 struct nvkm_pll_vals *pv) 205{ 206 struct nvkm_device *device = init->subdev.device; 207 int chip_version = device->bios->version.chip; 208 bool nv3035 = chip_version == 0x30 || chip_version == 0x35; 209 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); 210 uint32_t oldpll1 = nvkm_rd32(device, reg1); 211 uint32_t oldpll2 = !nv3035 ? nvkm_rd32(device, reg2) : 0; 212 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; 213 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; 214 uint32_t oldramdac580 = 0, ramdac580 = 0; 215 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */ 216 uint32_t saved_powerctrl_1 = 0, savedc040 = 0; 217 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); 218 219 /* model specific additions to generic pll1 and pll2 set up above */ 220 if (nv3035) { 221 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | 222 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4; 223 pll2 = 0; 224 } 225 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */ 226 oldramdac580 = nvkm_rd32(device, 0x680580); 227 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); 228 if (oldramdac580 != ramdac580) 229 oldpll1 = ~0; /* force mismatch */ 230 if (single_stage) 231 /* magic value used by nvidia in single stage mode */ 232 pll2 |= 0x011f; 233 } 234 if (chip_version > 0x70) 235 /* magic bits set by the blob (but not the bios) on g71-73 */ 236 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; 237 238 if (oldpll1 == pll1 && oldpll2 == pll2) 239 return; /* already set */ 240 241 if (shift_powerctrl_1 >= 0) { 242 saved_powerctrl_1 = nvkm_rd32(device, 0x001584); 243 nvkm_wr32(device, 0x001584, 244 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 245 1 << shift_powerctrl_1); 246 } 247 248 if (chip_version >= 0x40) { 249 int shift_c040 = 14; 250 251 switch (reg1) { 252 case 0x680504: 253 shift_c040 += 2; /* fall through */ 254 case 0x680500: 255 shift_c040 += 2; /* fall through */ 256 case 0x680520: 257 shift_c040 += 2; /* fall through */ 258 case 0x680508: 259 shift_c040 += 2; 260 } 261 262 savedc040 = nvkm_rd32(device, 0xc040); 263 if (shift_c040 != 14) 264 nvkm_wr32(device, 0xc040, savedc040 & ~(3 << shift_c040)); 265 } 266 267 if (oldramdac580 != ramdac580) 268 nvkm_wr32(device, 0x680580, ramdac580); 269 270 if (!nv3035) 271 nvkm_wr32(device, reg2, pll2); 272 nvkm_wr32(device, reg1, pll1); 273 274 if (shift_powerctrl_1 >= 0) 275 nvkm_wr32(device, 0x001584, saved_powerctrl_1); 276 if (chip_version >= 0x40) 277 nvkm_wr32(device, 0xc040, savedc040); 278} 279 280void 281setPLL_double_lowregs(struct nvkm_devinit *init, u32 NMNMreg, 282 struct nvkm_pll_vals *pv) 283{ 284 /* When setting PLLs, there is a merry game of disabling and enabling 285 * various bits of hardware during the process. This function is a 286 * synthesis of six nv4x traces, nearly each card doing a subtly 287 * different thing. With luck all the necessary bits for each card are 288 * combined herein. Without luck it deviates from each card's formula 289 * so as to not work on any :) 290 */ 291 struct nvkm_device *device = init->subdev.device; 292 uint32_t Preg = NMNMreg - 4; 293 bool mpll = Preg == 0x4020; 294 uint32_t oldPval = nvkm_rd32(device, Preg); 295 uint32_t NMNM = pv->NM2 << 16 | pv->NM1; 296 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | 297 0xc << 28 | pv->log2P << 16; 298 uint32_t saved4600 = 0; 299 /* some cards have different maskc040s */ 300 uint32_t maskc040 = ~(3 << 14), savedc040; 301 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; 302 303 if (nvkm_rd32(device, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval) 304 return; 305 306 if (Preg == 0x4000) 307 maskc040 = ~0x333; 308 if (Preg == 0x4058) 309 maskc040 = ~(0xc << 24); 310 311 if (mpll) { 312 struct nvbios_pll info; 313 uint8_t Pval2; 314 315 if (nvbios_pll_parse(device->bios, Preg, &info)) 316 return; 317 318 Pval2 = pv->log2P + info.bias_p; 319 if (Pval2 > info.max_p) 320 Pval2 = info.max_p; 321 Pval |= 1 << 28 | Pval2 << 20; 322 323 saved4600 = nvkm_rd32(device, 0x4600); 324 nvkm_wr32(device, 0x4600, saved4600 | 8 << 28); 325 } 326 if (single_stage) 327 Pval |= mpll ? 1 << 12 : 1 << 8; 328 329 nvkm_wr32(device, Preg, oldPval | 1 << 28); 330 nvkm_wr32(device, Preg, Pval & ~(4 << 28)); 331 if (mpll) { 332 Pval |= 8 << 20; 333 nvkm_wr32(device, 0x4020, Pval & ~(0xc << 28)); 334 nvkm_wr32(device, 0x4038, Pval & ~(0xc << 28)); 335 } 336 337 savedc040 = nvkm_rd32(device, 0xc040); 338 nvkm_wr32(device, 0xc040, savedc040 & maskc040); 339 340 nvkm_wr32(device, NMNMreg, NMNM); 341 if (NMNMreg == 0x4024) 342 nvkm_wr32(device, 0x403c, NMNM); 343 344 nvkm_wr32(device, Preg, Pval); 345 if (mpll) { 346 Pval &= ~(8 << 20); 347 nvkm_wr32(device, 0x4020, Pval); 348 nvkm_wr32(device, 0x4038, Pval); 349 nvkm_wr32(device, 0x4600, saved4600); 350 } 351 352 nvkm_wr32(device, 0xc040, savedc040); 353 354 if (mpll) { 355 nvkm_wr32(device, 0x4020, Pval & ~(1 << 28)); 356 nvkm_wr32(device, 0x4038, Pval & ~(1 << 28)); 357 } 358} 359 360int 361nv04_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq) 362{ 363 struct nvkm_subdev *subdev = &devinit->subdev; 364 struct nvkm_bios *bios = subdev->device->bios; 365 struct nvkm_pll_vals pv; 366 struct nvbios_pll info; 367 int cv = bios->version.chip; 368 int N1, M1, N2, M2, P; 369 int ret; 370 371 ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info); 372 if (ret) 373 return ret; 374 375 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); 376 if (!ret) 377 return -EINVAL; 378 379 pv.refclk = info.refclk; 380 pv.N1 = N1; 381 pv.M1 = M1; 382 pv.N2 = N2; 383 pv.M2 = M2; 384 pv.log2P = P; 385 386 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 387 cv >= 0x40) { 388 if (type > 0x405c) 389 setPLL_double_highregs(devinit, type, &pv); 390 else 391 setPLL_double_lowregs(devinit, type, &pv); 392 } else 393 setPLL_single(devinit, type, &pv); 394 395 return 0; 396} 397 398int 399nv04_devinit_post(struct nvkm_devinit *init, bool execute) 400{ 401 return nvbios_post(&init->subdev, execute); 402} 403 404void 405nv04_devinit_preinit(struct nvkm_devinit *base) 406{ 407 struct nv04_devinit *init = nv04_devinit(base); 408 struct nvkm_subdev *subdev = &init->base.subdev; 409 struct nvkm_device *device = subdev->device; 410 411 /* make i2c busses accessible */ 412 nvkm_mask(device, 0x000200, 0x00000001, 0x00000001); 413 414 /* unslave crtcs */ 415 if (init->owner < 0) 416 init->owner = nvkm_rdvgaowner(device); 417 nvkm_wrvgaowner(device, 0); 418 419 if (!init->base.post) { 420 u32 htotal = nvkm_rdvgac(device, 0, 0x06); 421 htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x01) << 8; 422 htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x20) << 4; 423 htotal |= (nvkm_rdvgac(device, 0, 0x25) & 0x01) << 10; 424 htotal |= (nvkm_rdvgac(device, 0, 0x41) & 0x01) << 11; 425 if (!htotal) { 426 nvkm_debug(subdev, "adaptor not initialised\n"); 427 init->base.post = true; 428 } 429 } 430} 431 432void * 433nv04_devinit_dtor(struct nvkm_devinit *base) 434{ 435 struct nv04_devinit *init = nv04_devinit(base); 436 /* restore vga owner saved at first init */ 437 nvkm_wrvgaowner(init->base.subdev.device, init->owner); 438 return init; 439} 440 441int 442nv04_devinit_new_(const struct nvkm_devinit_func *func, 443 struct nvkm_device *device, int index, 444 struct nvkm_devinit **pinit) 445{ 446 struct nv04_devinit *init; 447 448 if (!(init = kzalloc(sizeof(*init), GFP_KERNEL))) 449 return -ENOMEM; 450 *pinit = &init->base; 451 452 nvkm_devinit_ctor(func, device, index, &init->base); 453 init->owner = -1; 454 return 0; 455} 456 457static const struct nvkm_devinit_func 458nv04_devinit = { 459 .dtor = nv04_devinit_dtor, 460 .preinit = nv04_devinit_preinit, 461 .post = nv04_devinit_post, 462 .meminit = nv04_devinit_meminit, 463 .pll_set = nv04_devinit_pll_set, 464}; 465 466int 467nv04_devinit_new(struct nvkm_device *device, int index, 468 struct nvkm_devinit **pinit) 469{ 470 return nv04_devinit_new_(&nv04_devinit, device, index, pinit); 471} 472