1/* $NetBSD: nouveau_nvkm_engine_gr_tu102.c,v 1.3 2021/12/19 10:51:57 riastradh Exp $ */ 2 3/* 4 * Copyright 2019 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24#include <sys/cdefs.h> 25__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_tu102.c,v 1.3 2021/12/19 10:51:57 riastradh Exp $"); 26 27#include "gf100.h" 28#include "ctxgf100.h" 29 30#include <nvif/class.h> 31 32#include <linux/nbsd-namespace.h> 33 34static void 35tu102_gr_init_fecs_exceptions(struct gf100_gr *gr) 36{ 37 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006f0002); 38} 39 40static void 41tu102_gr_init_fs(struct gf100_gr *gr) 42{ 43 struct nvkm_device *device = gr->base.engine.subdev.device; 44 int sm; 45 46 gp100_grctx_generate_smid_config(gr); 47 gk104_grctx_generate_gpc_tpc_nr(gr); 48 49 for (sm = 0; sm < gr->sm_nr; sm++) { 50 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + 51 gr->sm[sm].tpc * 4), sm); 52 } 53 54 gm200_grctx_generate_dist_skip_table(gr); 55 gf100_gr_init_num_tpc_per_gpc(gr, true, true); 56} 57 58static void 59tu102_gr_init_zcull(struct gf100_gr *gr) 60{ 61 struct nvkm_device *device = gr->base.engine.subdev.device; 62 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); 63 const u8 tile_nr = ALIGN(gr->tpc_total, 64); 64 u8 bank[GPC_MAX] = {}, gpc, i, j; 65 u32 data; 66 67 for (i = 0; i < tile_nr; i += 8) { 68 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { 69 data |= bank[gr->tile[i + j]] << (j * 4); 70 bank[gr->tile[i + j]]++; 71 } 72 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data); 73 } 74 75 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 76 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), 77 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); 78 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | 79 gr->tpc_total); 80 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); 81 } 82 83 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); 84} 85 86static void 87tu102_gr_init_gpc_mmu(struct gf100_gr *gr) 88{ 89 struct nvkm_device *device = gr->base.engine.subdev.device; 90 91 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff); 92 nvkm_wr32(device, 0x418890, 0x00000000); 93 nvkm_wr32(device, 0x418894, 0x00000000); 94 95 nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); 96 nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); 97 nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); 98} 99 100static const struct gf100_gr_func 101tu102_gr = { 102 .oneinit_tiles = gm200_gr_oneinit_tiles, 103 .oneinit_sm_id = gm200_gr_oneinit_sm_id, 104 .init = gf100_gr_init, 105 .init_419bd8 = gv100_gr_init_419bd8, 106 .init_gpc_mmu = tu102_gr_init_gpc_mmu, 107 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master, 108 .init_zcull = tu102_gr_init_zcull, 109 .init_num_active_ltcs = gf100_gr_init_num_active_ltcs, 110 .init_rop_active_fbps = gp100_gr_init_rop_active_fbps, 111 .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask, 112 .init_fs = tu102_gr_init_fs, 113 .init_fecs_exceptions = tu102_gr_init_fecs_exceptions, 114 .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2, 115 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr, 116 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, 117 .init_504430 = gv100_gr_init_504430, 118 .init_shader_exceptions = gv100_gr_init_shader_exceptions, 119 .trap_mp = gv100_gr_trap_mp, 120 .rops = gm200_gr_rops, 121 .gpc_nr = 6, 122 .tpc_nr = 5, 123 .ppc_nr = 3, 124 .grctx = &tu102_grctx, 125 .zbc = &gp102_gr_zbc, 126 .sclass = { 127 { -1, -1, FERMI_TWOD_A }, 128 { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, 129 { -1, -1, TURING_A, &gf100_fermi }, 130 { -1, -1, TURING_COMPUTE_A }, 131 {} 132 } 133}; 134 135MODULE_FIRMWARE("nvidia/tu102/gr/fecs_bl.bin"); 136MODULE_FIRMWARE("nvidia/tu102/gr/fecs_inst.bin"); 137MODULE_FIRMWARE("nvidia/tu102/gr/fecs_data.bin"); 138MODULE_FIRMWARE("nvidia/tu102/gr/fecs_sig.bin"); 139MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_bl.bin"); 140MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_inst.bin"); 141MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_data.bin"); 142MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_sig.bin"); 143MODULE_FIRMWARE("nvidia/tu102/gr/sw_ctx.bin"); 144MODULE_FIRMWARE("nvidia/tu102/gr/sw_nonctx.bin"); 145MODULE_FIRMWARE("nvidia/tu102/gr/sw_bundle_init.bin"); 146MODULE_FIRMWARE("nvidia/tu102/gr/sw_method_init.bin"); 147 148MODULE_FIRMWARE("nvidia/tu104/gr/fecs_bl.bin"); 149MODULE_FIRMWARE("nvidia/tu104/gr/fecs_inst.bin"); 150MODULE_FIRMWARE("nvidia/tu104/gr/fecs_data.bin"); 151MODULE_FIRMWARE("nvidia/tu104/gr/fecs_sig.bin"); 152MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_bl.bin"); 153MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_inst.bin"); 154MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_data.bin"); 155MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_sig.bin"); 156MODULE_FIRMWARE("nvidia/tu104/gr/sw_ctx.bin"); 157MODULE_FIRMWARE("nvidia/tu104/gr/sw_nonctx.bin"); 158MODULE_FIRMWARE("nvidia/tu104/gr/sw_bundle_init.bin"); 159MODULE_FIRMWARE("nvidia/tu104/gr/sw_method_init.bin"); 160 161MODULE_FIRMWARE("nvidia/tu106/gr/fecs_bl.bin"); 162MODULE_FIRMWARE("nvidia/tu106/gr/fecs_inst.bin"); 163MODULE_FIRMWARE("nvidia/tu106/gr/fecs_data.bin"); 164MODULE_FIRMWARE("nvidia/tu106/gr/fecs_sig.bin"); 165MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_bl.bin"); 166MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_inst.bin"); 167MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_data.bin"); 168MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_sig.bin"); 169MODULE_FIRMWARE("nvidia/tu106/gr/sw_ctx.bin"); 170MODULE_FIRMWARE("nvidia/tu106/gr/sw_nonctx.bin"); 171MODULE_FIRMWARE("nvidia/tu106/gr/sw_bundle_init.bin"); 172MODULE_FIRMWARE("nvidia/tu106/gr/sw_method_init.bin"); 173 174MODULE_FIRMWARE("nvidia/tu117/gr/fecs_bl.bin"); 175MODULE_FIRMWARE("nvidia/tu117/gr/fecs_inst.bin"); 176MODULE_FIRMWARE("nvidia/tu117/gr/fecs_data.bin"); 177MODULE_FIRMWARE("nvidia/tu117/gr/fecs_sig.bin"); 178MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_bl.bin"); 179MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_inst.bin"); 180MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_data.bin"); 181MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_sig.bin"); 182MODULE_FIRMWARE("nvidia/tu117/gr/sw_ctx.bin"); 183MODULE_FIRMWARE("nvidia/tu117/gr/sw_nonctx.bin"); 184MODULE_FIRMWARE("nvidia/tu117/gr/sw_bundle_init.bin"); 185MODULE_FIRMWARE("nvidia/tu117/gr/sw_method_init.bin"); 186 187MODULE_FIRMWARE("nvidia/tu116/gr/fecs_bl.bin"); 188MODULE_FIRMWARE("nvidia/tu116/gr/fecs_inst.bin"); 189MODULE_FIRMWARE("nvidia/tu116/gr/fecs_data.bin"); 190MODULE_FIRMWARE("nvidia/tu116/gr/fecs_sig.bin"); 191MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_bl.bin"); 192MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_inst.bin"); 193MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_data.bin"); 194MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_sig.bin"); 195MODULE_FIRMWARE("nvidia/tu116/gr/sw_ctx.bin"); 196MODULE_FIRMWARE("nvidia/tu116/gr/sw_nonctx.bin"); 197MODULE_FIRMWARE("nvidia/tu116/gr/sw_bundle_init.bin"); 198MODULE_FIRMWARE("nvidia/tu116/gr/sw_method_init.bin"); 199 200static const struct gf100_gr_fwif 201tu102_gr_fwif[] = { 202 { 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, 203 {} 204}; 205 206int 207tu102_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) 208{ 209 return gf100_gr_new_(tu102_gr_fwif, device, index, pgr); 210} 211